[CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing

[Peter Arremann]

On Friday 24 June 2005 02:09, Bryan J. Smith wrote:
> Normally the 32-bit Athlon is limited in its addressing to 32-bit/PAE36
> (4/64GiB) for Intel GTL compatibility at the BIOS, OS, etc...  If you
> have a BIOS that lets the 32-bit Athlon break 32-bit/PAE36 Intel GTL
> compatibility, and pair it with an OS that does the same, then you can
> have the _full_ support of 32-bit Athlon's EV6 addressing architecture.
> In fact, EV6 is _nothing_ like GTL, but it just emulates it.  That
> includes it looking like a "SMP bus" in the case of Athlon MP, when --
> in fact -- it's an "MP switch."
Hmmm - The GTL bus uses 36bit for address... So if you get a license from 
Intel and build your own device, it can address 36bits directly without any 
games. PAE36 is a mmu concept that allows a 32 bit OS to have 16 4GB pages 
(hence the name Page Address Extensions 36 bits...) 

So if you have a 32 bit athlon, you get 4GB ram... To go above that, you need 
more bits. Those bits need to be stored in a separate register since all your 
apps and os only have 32bit - and then you need to have a mmu that can 
combine those two into the physical address... And the combining of an offset 
and a segment is what PAE36 is all about... See where my confusion comes 
in? :-) 


> If you want to know more about the non-PAE36 >4GB Linux hack and the few
> Athlon MP mainboards with BIOSes that support it, read up on the LKML
> circa February 2004.
Sorry to make you even more work but I searched the LKML archives and couldn't 
find anything :-( Could you please send me a direct link?

Peter.