[CentOS] Re: OT: Google Earth, v.4.3.7284.3916 (beta) on CentOS 5.2 (32 bit)

Scott Silva ssilva at sgvwater.com
Mon Aug 25 18:43:35 UTC 2008


on 8-23-2008 12:08 PM Lanny Marcus spake the following:
> On Fri, Aug 22, 2008 at 8:34 PM, John R Pierce <pierce-BRp9yk6zKL1Wk0Htik3J/w at public.gmane.org> wrote:
>> Lanny Marcus wrote:
>>>  Question: How do I
>>> determine whether or not the CPU in this box (I think it's an Intel
>>> Celeron 2.6 GHz) supports SSE2 or not? I suspect the CPU does *not*
>>> support SSE2.
>> this gets fun.  AFAIK, there's several generations of Celerons and its quite
>> frustrating to tell them apart from purely a clock speed.
>>
>> The original Celerons were based on cache reduced P2 Deschutes, and later P3
>> Coppermine, these had 66Mhz busses, and used socket 370 (or even Slot 1 for
>> the oldest versions).   These had MMX and/or SSE depending on the age.
>>
>> there were Celerons from 2.0 to 2.8Ghz that were 478 pin 400Mhz FSB, and P4
>> "Northwood" generation technology.    I do believe these are  SSE2 but I'm
>> having trouble finding definitive documentation of this.
>>
>> there are also Celeron "D" that are Prescott and can be either socket 478 or
>> LGA775 and run from 2.13 up to 3.33Ghz, using a 533Mhz FSB, these have SSE3.
>>
>> and nowdays, there are celerons that are based on Core....   really really
>> confusing.
> 
> John: Thank you for the above explanation! As I just posted, in my
> reply to Bill, the CPU has a flag for SSE2. I suspect that means that
> the
> chip does support SSE2. If so, the latest version of Google Earth
> wouldn't run properly on it. Lanny
Celerons in the last few years are usually just re-branded older generation 
chips so they can extend the manufacturing cycles of their silicon plants.
Every new generation of chips is almost always followed by a new line of 
celerons with some crippling like smaller cache or clock speed locking based 
on a previous generations chip.

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