<br><br><div class="gmail_quote">2011/3/22 <span dir="ltr"><<a href="mailto:m.roth@5-cent.us">m.roth@5-cent.us</a>></span><br><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div class="im">Vladimir Budnev wrote:<br>
> 2011/3/22 <<a href="mailto:m.roth@5-cent.us">m.roth@5-cent.us</a>><br>
>> Vladimir Budnev wrote:<br>
>> > 2011/3/22 <<a href="mailto:m.roth@5-cent.us">m.roth@5-cent.us</a>><br>
>> >> Vladimir Budnev wrote:<br>
>> >> > 2011/3/21 <<a href="mailto:m.roth@5-cent.us">m.roth@5-cent.us</a>><br>
>> >> >> Vladimir Budnev wrote:<br>
>> >> >> ><br>
>> >> >> > We are running, Centos 4.8 on SuperMicro SYS-6026T-3RF with<br>
>> >> >> > 2xIntel Xeon E5630 and 8xKingston KVR1333D3D4R9S/4G<br>
>> >> >> ><br>
>> >> >> > For some time we have lots of MCE in mcelog and we cant find out<br>
>> >> >> > the reason.<br>
>> >> >><br>
>> >> >> The only thing that shows there (when it shows, since sometimes it<br>
>> >> >> doesn't seem to) is a hardware error. You *WILL* be replacing<br>
>> >> >> hardware, sometime soon, like yesterday.<br>
>> >> <snip><br>
</div><div class="im">>> > We have 2 quad core proc, so 8 cpu. 1/8=0 Is it cpu-a1 slot or<br>
depends on<br>
>> > situation? I hope we will find those bustards ourselvs but hint would<br>
>> > be great.<br>
>> ><br>
>> > And one more thing i cant funderstand ... if there is,say, 8 "cpu<br>
>> > numbers" per each memory module(in our situation), why we see only 4<br>
numbers<br>
>> > and not 8 e.g. 0,1,2,3,4,5,6,7 ?<br>
>><br>
>> I'm now confused about a lot: originally, you mentioned 53 - 57, was it?<br>
>> That doesn't add up, since you say you have 2 quad core processors, for<br>
>> a total of 8 cpus, and each of those processors have 6 banks, which would<br>
>> mean each processor should only see six (directly). Where I'm confused<br>
>> is how you could have cores 32-35, or 53-whatsit, when you only have 8<br>
>> cores in two processors.<br>
><br>
> 2 cpu each 8 cores and HT support. So 16 at max i think. for such way is<br>
> it ok?<br>
<br>
</div>Huh? Above, you say "2 quad core proc" - that's 8 cores over two processor<br>
chips. HT support doesn't figure into it; if you use dmidecode or lshw, I<br>
believe it will show you 8 cores, not 16.<br></blockquote><div>Was a typo, sorry. 2 CPU and each one has 4 cores so totally 8 cores.<br><br></div><blockquote class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt 0.8ex; padding-left: 1ex;">
<div class="im"><br>
> I really lost the idea line with those cpu to memory bank mappings...<br>
<br>
</div>Each processor will directly see the DIMMs associate with it, so that the<br>
banks associated with each processor will be what directly affects the<br>
cores. So, if you see something like<br>
Mar 20 05:01:35 <system name> kernel: Northbridge Error, node 0, core: 5<br>
(these processors are 8-core), it means that one of the DIMMs in bank 0,<br>
0-3, is bad.<br>
You should see<br>
__<br>
|_0| 0 1 2 3<br>
__<br>
|_1| 0 1 2 3<br>
<br>
or whatever on the m/b, so one of the top ones there is affected. Is that<br>
any clearer?</blockquote><div>First of all big thnx for helping mark.<br><br></div><div>In your example everything is ok. But i am lost with what we have.<br>Previously we recieved messages like i post in the first mail:<br>
CPU 51 BANK 8 TSC 8511e3ca77dc <br>MISC 274d587f00006141 ADDR 807044840 <br>STATUS cc0055000001009f MCGSTATU<br><br>And always there were same cpu numbers. I really dont know why do mcleog show such numbers but thats what we have.Always Bank 8 and there were 32,33,34,45 and 50,51,52,53 numbers in CPU field.<br>
<br>You encouraged us that it is a dimm problem and we decide to make a little research which i described up the thread. During that wev replaced DIMM moduels between slots, so now we have BANK 8 and cpu 1,2,3 and 18,29,20,21. It really seems that some how those numbers connected with RAM modules.<br>
<br>But... as i sad we have following slots<br> CPU1 cpu1-a1 cpu1-a2 cpu1-a3 cpu1-b1 cpu1-b2 cpu1-b3<br> CPU2 cpu2-a1 cpu2-a2 cpu2-a3 cpu2-b1 cpu2-b2 cpu2-b3<br><br>We have modules placed in such way:<br>+------------+------------+------------+------------+------------+------------+------------+<br>
| | V | V | V | V | free | free |<br>+------------+------------+------------+------------+------------+------------+------------+<br>| CPU1 | cpu1-a1| cpu1-a2 | cpu1-a3 | cpu1-b1 | cpu1-b2| cpu1-b3 |<br>
+------------+------------+------------+------------+------------+------------+------------+<br><br><br>
+------------+------------+------------+------------+------------+------------+------------+<br>
| | V | V | V | V | free | free |<br>
+------------+------------+------------+------------+------------+------------+------------+<br>
| CPU2 | cpu2-a1| cpu2-a2 | cpu2-a3 | cpu2-b1 | cpu1-b2| cpu1-b3 |<br>
+------------+------------+------------+------------+------------+------------+------------+<br><br>Definetely there is something with memory banks,becasue replacinbg moudels changed the mce messages, but what exactly...or iv interpreted all wrong?<br>
<br><br> </div></div>