According dmidecode this cpu have:<br>L1 - 64KiB - not true in my opinion because (L1 Instruction cache: 32KB and L1 Data cache: 32KB) per core - L1 should be 128KiB<br>L2 - 6Mib - true<br><br><br><br><br>dmidecode --type 4,7<br>
# dmidecode 2.10<br>SMBIOS 2.4 present.<br><br>Handle 0x0004, DMI type 4, 35 bytes<br>Processor Information<br> Socket Designation: U10<br> Type: Central Processor<br> Family: Pentium M<br> Manufacturer: Intel(R)<br>
ID: 76 06 01 00 FF FB EB BF<br> Signature: Type 0, Family 6, Model 23, Stepping 6<br> Flags:<br> FPU (Floating-point unit on-chip)<br> VME (Virtual mode extension)<br> DE (Debugging extension)<br>
PSE (Page size extension)<br> TSC (Time stamp counter)<br> MSR (Model specific registers)<br> PAE (Physical address extension)<br> MCE (Machine check exception)<br>
CX8 (CMPXCHG8 instruction supported)<br> APIC (On-chip APIC hardware supported)<br> SEP (Fast system call)<br> MTRR (Memory type range registers)<br> PGE (Page global enable)<br>
MCA (Machine check architecture)<br> CMOV (Conditional move instruction supported)<br> PAT (Page attribute table)<br> PSE-36 (36-bit page size extension)<br> CLFSH (CLFLUSH instruction supported)<br>
DS (Debug store)<br> ACPI (ACPI supported)<br> MMX (MMX technology supported)<br> FXSR (Fast floating-point save and restore)<br> SSE (Streaming SIMD extensions)<br>
SSE2 (Streaming SIMD extensions 2)<br> SS (Self-snoop)<br> HTT (Hyper-threading technology)<br> TM (Thermal monitor supported)<br> PBE (Pending break enabled)<br>
Version: Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz<br> Voltage: 1.1 V<br> External Clock: 200 MHz<br> Max Speed: 2500 MHz<br> Current Speed: 2500 MHz<br> Status: Populated, Enabled<br>
Upgrade: None<br> L1 Cache Handle: 0x0005<br> L2 Cache Handle: 0x0006<br> L3 Cache Handle: Not Provided<br> Serial Number: Not Specified<br> Asset Tag: Not Specified<br> Part Number: Not Specified<br>
<br>Handle 0x0005, DMI type 7, 19 bytes<br>Cache Information<br> Socket Designation: Internal L1 Cache<br> Configuration: Enabled, Not Socketed, Level 1<br> Operational Mode: Write Back<br> Location: Internal<br>
Installed Size: 64 kB<br> Maximum Size: 64 kB<br> Supported SRAM Types:<br> Burst<br> Installed SRAM Type: Burst<br> Speed: Unknown<br> Error Correction Type: Unknown<br>
System Type: Unified<br> Associativity: 4-way Set-associative<br><br>Handle 0x0006, DMI type 7, 19 bytes<br>Cache Information<br> Socket Designation: Internal L2 Cache<br> Configuration: Enabled, Not Socketed, Level 2<br>
Operational Mode: Write Back<br> Location: External<br> Installed Size: 6144 kB<br> Maximum Size: 6144 kB<br> Supported SRAM Types:<br> Burst<br> Installed SRAM Type: Burst<br>
Speed: Unknown<br> Error Correction Type: None<br> System Type: Unified<br> Associativity: 4-way Set-associative<br><br><br><div class="gmail_quote">On Mon, Jun 27, 2011 at 1:00 PM, William L. Maltby <span dir="ltr"><<a href="mailto:CentOS4Bill@triad.rr.com">CentOS4Bill@triad.rr.com</a>></span> wrote:<br>
<blockquote class="gmail_quote" style="margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;"><div class="im"><br>
On Mon, 2011-06-27 at 12:25 +0200, clibup clibup wrote:<br>
> Hi<br>
><br>
> Could anybody explain me how to check how many L1/L2 cache my cpu<br>
> have.<br>
> I'm using CentOS 5.6<br>
<br>
</div>On my workstation, type 4 is cpu, 7 is cache. W/no params list<br>
everything.<br>
<br>
# dmidecode --type 4,7<br>
<br>
><br>
> <snip><br>
<br>
Bill<br>
<br>
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</blockquote></div><br>