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    Try this:<br>
    <br>
    <a class="moz-txt-link-freetext" href="http://www.open-mpi.org/software/hwloc/v1.0/">http://www.open-mpi.org/software/hwloc/v1.0/</a><br>
    <br>
    On 27/06/2011 13:25, clibup clibup wrote:
    <blockquote
      cite="mid:BANLkTik+nYXqbwJ7iBh-ZdtG+maXgKxnRQ@mail.gmail.com"
      type="cite">Hi<br>
      <br>
      Could anybody explain me how to check how many L1/L2 cache my cpu
      have.<br>
      I'm using CentOS 5.6<br>
      <style type="text/css">p { margin-bottom: 0.21cm; }</style>
      <p style="margin-bottom: 0cm;"><b>cat /proc/cpuinfo |grep CPU
        </b></p>
      <p style="margin-bottom: 0cm;">model name : Intel(R) Core(TM)2
        Duo CPU T9300 @ 2.50GHz
      </p>
      <p style="margin-bottom: 0cm;">model name : Intel(R) Core(TM)2
        Duo CPU T9300 @ 2.50GHz
      </p>
      <p style="margin-bottom: 0cm; font-weight: normal;">Diagram of a
        generic dual-core processor, with CPU-local level 1 caches, and
        a
        shared, on-die level 2 cache.</p>
      <p style="margin-bottom: 0cm;"><b><a moz-do-not-send="true"
href="http://upload.wikimedia.org/wikipedia/commons/e/ec/Dual_Core_Generic.svg">http://upload.wikimedia.org/wikipedia/commons/e/ec/Dual_Core_Generic.svg</a></b></p>
      <br>
      #########################<br>
      >From /proc/cpuinfo we see that CPU have 6MB L2 cache, but we
      see it doubled and it's not true because according Intel
      specification we know that this CPU have shared L2 cache.<br>
      <p style="margin-bottom: 0cm;"><b>grep 'cache size' /proc/cpuinfo
        </b></p>
      <p style="margin-bottom: 0cm;">cache size : 6144 KB
      </p>
      <p style="margin-bottom: 0cm;">cache size : 6144 KB
      </p>
      <p style="margin-bottom: 0cm;">###################################<br>
      </p>
      <p style="margin-bottom: 0cm;">Here we can see that cpu have 6MiB
        L2 cache and 64KiB L1 cache</p>
      <p style="margin-bottom: 0cm;"><b>dmesg |grep 'CPU: L'
        </b></p>
      <p style="margin-bottom: 0cm;">CPU: L1 I cache: 32K, L1 D cache:
        32K
      </p>
      <p style="margin-bottom: 0cm;">CPU: L2 cache: 6144K
      </p>
      <p style="margin-bottom: 0cm;"><br>
      </p>
      <p style="margin-bottom: 0cm;">L2 - true</p>
      <p style="margin-bottom: 0cm;">L1 - not true because each CPU core
        have 64 KiB memory cache (Instruction and Data)<br>
      </p>
      <p style="margin-bottom: 0cm;">
      </p>
      <p style="margin-bottom: 0cm;">############################################<br>
      </p>
      <p style="margin-bottom: 0cm;">Into sys directory we can find some
        information about cache size but again not all information are
        true</p>
      <p style="margin-bottom: 0cm;">L2 - not true <br>
      </p>
      <p style="margin-bottom: 0cm;">
        L1 - true<br>
      </p>
      <p style="margin-bottom: 0cm;"><b>cat
          /sys/devices/system/cpu/cpu*/cache/index*/size </b></p>
      <p style="margin-bottom: 0cm;">32K
      </p>
      <p style="margin-bottom: 0cm;">32K
      </p>
      <p style="margin-bottom: 0cm;">6144K
      </p>
      <p style="margin-bottom: 0cm;">32K
      </p>
      <p style="margin-bottom: 0cm;">32K
      </p>
      <p style="margin-bottom: 0cm;">6144K
      </p>
      <p style="margin-bottom: 0cm;">#####################################</p>
      <p style="margin-bottom: 0cm;">getconf show information only for
        one core.<br>
      </p>
      <p style="margin-bottom: 0cm;"><b>getconf -a |grep CACHE
        </b></p>
      <p style="margin-bottom: 0cm;">LEVEL1_ICACHE_SIZE 32768
      </p>
      <p style="margin-bottom: 0cm;">LEVEL1_DCACHE_SIZE 32768
      </p>
      <p style="margin-bottom: 0cm;">LEVEL2_CACHE_SIZE 6291456
      </p>
      <p style="margin-bottom: 0cm;"><br>
      </p>
      <p style="margin-bottom: 0cm;">L1 - 64KiB - not true</p>
      <p style="margin-bottom: 0cm;">L2 - 6MiB - true<br>
      </p>
      <p style="margin-bottom: 0cm;">############################</p>
      <p style="margin-bottom: 0cm;">According the most powerful tool -
        x86info we can presume that we have:</p>
      <p style="margin-bottom: 0cm;">
      </p>
      <p style="margin-bottom: 0cm;"><b>x86info -c
        </b></p>
      <p style="margin-bottom: 0cm;"><br>
      </p>
      <p style="margin-bottom: 0cm;">Found 2 identical CPUs
      </p>
      <p style="margin-bottom: 0cm;">Extended Family: 0 Extended Model:
        1
        Family: 6 Model: 23 Stepping: 6
      </p>
      <p style="margin-bottom: 0cm;">Type: 0 (Original OEM)
      </p>
      <p style="margin-bottom: 0cm;">CPU Model (x86info's best guess):
        Core
        2 Duo P8600
      </p>
      <p style="margin-bottom: 0cm;">Processor name string (BIOS
        programmed): Intel(R) Core(TM)2 Duo CPU T9300 @ 2.50GHz
      </p>
      <p style="margin-bottom: 0cm;">
      </p>
      <p style="margin-bottom: 0cm;">Cache info
      </p>
      <p style="margin-bottom: 0cm;"> L1 Instruction cache: 32KB, 8-way
        associative. 64 byte line size.
      </p>
      <p style="margin-bottom: 0cm;"> L1 Data cache: 32KB, 8-way
        associative. 64 byte line size.
      </p>
      <p style="margin-bottom: 0cm;"> L2 cache: 6MB, 24-way set
        associative,
        64-byte line size.
      </p>
      <p style="margin-bottom: 0cm;">TLB info
      </p>
      <p style="margin-bottom: 0cm;"> Instruction TLB: 4x 4MB page
        entries,
        or 8x 2MB pages entries, 4-way associative
      </p>
      <p style="margin-bottom: 0cm;"> Instruction TLB: 4K pages, 4-way
        associative, 128 entries.
      </p>
      <p style="margin-bottom: 0cm;"> Data TLB: 4MB pages, 4-way
        associative, 32 entries
      </p>
      <p style="margin-bottom: 0cm;"> L1 Data TLB: 4KB pages, 4-way set
        associative, 16 entries
      </p>
      <p style="margin-bottom: 0cm;"> L1 Data TLB: 4MB pages, 4-way set
        associative, 16 entries
      </p>
      <p style="margin-bottom: 0cm;"> Data TLB: 4K pages, 4-way
        associative,
        256 entries.
      </p>
      <p style="margin-bottom: 0cm;"> 64 byte prefetching.
      </p>
      <p style="margin-bottom: 0cm;">Total processor threads: 2
      </p>
      <p style="margin-bottom: 0cm;">This system has 1 dual-core
        processor
        running at an estimated 2.50GHz <br>
      </p>
      <p style="margin-bottom: 0cm;"><br>
      </p>
      <p style="margin-bottom: 0cm;">L1 - 128Kib - true<br>
      </p>
      <p style="margin-bottom: 0cm;">L2 - 12 MiB - not true</p>
      ##########################<br>
      Output form dmidecode is useless.<br>
      <br>
      dmidecode -t processor<br>
       L1 Cache Handle: 0x0005<br>
       L2 Cache Handle: 0x0006<br>
       L3 Cache Handle: Not Provided<br>
      <br>
      ##################################<br>
      Is there any tool which can clearly indicate how many L1/L2 cache
      cpu have.<br>
      <br>
      If someone have any idea how to clearly designate L1/L2 cache
      don't hesitate share your knowledge .. ;)<br>
      P.S.<br>
      Sorry for my English ...<br>
      <br>
      <br>
      Regards<br>
      <br>
      <br>
      <br>
      <pre wrap="">
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</pre>
    </blockquote>
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