- Discuss - lists.centos.org

Re: Hot swap CPU
by Bryan J. Smith <b.j.smith＠ieee.org> 29 Jun '05

29 Jun '05

From: Rodrigo Barbosa <rodrigob(a)suespammers.org> > Memory hotswap ? Sounds fishy to me, at least on IA32{,e} > platforms. Are you sure about that ? Yes. They are proprietary NUMA implementations of both IA-32 Xeon and IA-64 Itanium that allow all sorts of swapping, largley via a daughtercard (i.e., the memory comes out with the CPU on a single board). In reality, this is really an area where Blades are more manageable for far less cost though. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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RE: [CentOS] 4.1 beta for Alpha platform
by Mark A. Lewis 29 Jun '05

29 Jun '05

If someone can send me a link to the torrent, I can put it on an FTP. I am anxious to try it too. > -----Original Message----- > From: centos-bounces(a)centos.org > [mailto:centos-bounces@centos.org] On Behalf Of Lamar Owen > Sent: Wednesday, June 29, 2005 2:29 PM > To: CentOS mailing list > Subject: Re: [CentOS] 4.1 beta for Alpha platform > > > > Hi all, > > > > I have tried to install this beta release on PWS 433 au > but I can not > > boot /kernels/vmlinux.gz image. Error > > is: "unsupported compressed image". Is not posible to > install under > > this Alpha model?? > > Does anyone have an ftpable mirror of this yet? Bittorrent > is great, except when you don't allow it. While I could > loophole my own policy, I shouldn't. > -- > Lamar Owen > Director of Information Technology > Pisgah Astronomical Research Institute > 1 PARI Drive > Rosman, NC 28772 > (828)862-5554 > www.pari.edu > _______________________________________________ > CentOS mailing list > CentOS(a)centos.org > http://lists.centos.org/mailman/listinfo/centos > > -- > This message has been scanned for viruses and dangerous > content by MailScanner, and is believed to be clean. > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.

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autofs handling of nis maps - Centos4
by Hilliard, Jay 29 Jun '05

29 Jun '05

I have the following nis map (auto.facvs) * -vers=3 &:/disk1 Which allows hosts that have /disk1 exported to be mounted to /facvs/$hostname It works fine, but on Centos4, it allows me to cd /facvs/foo (where foo isn't a real host out there) I find it has mounted my local /disk1 as /facvs/foo. It seems to be ignoring the key in the map pertaining to the host if it's not a valid host. Does anyone know of a way to make it restrictive again and fail the mount if the hostname match isn't valid? -- Jay Hilliard Sr. Systems Administrator Disney Feature Animation

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RE: [CentOS] Hot swap CPU
by Mark A. Lewis 29 Jun '05

29 Jun '05

Compaq/HP Proliant DL580/DL760 both have this. > -----Original Message----- > From: centos-bounces(a)centos.org > [mailto:centos-bounces@centos.org] On Behalf Of Rodrigo Barbosa > Sent: Wednesday, June 29, 2005 1:13 PM > To: CentOS mailing list > Subject: Re: [CentOS] Hot swap CPU > > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > On Wed, Jun 29, 2005 at 12:59:24PM -0500, Bryan J. Smith > <b.j.smith(a)ieee.org> wrote: > > From: Rodrigo Barbosa <rodrigob(a)suespammers.org> > > > Btw, don't quote me on this one :) > > > I'm only 90% sure of the hotswapping capabilities, and > less than 50% > > > sure about the price :) > > > > There _are_ systems with hot-swap CPUs, memory and/or, > PCI[-X] slots. > > They are _not_ commodity and pricey, and require OS-level support. > > > > In fact, I believe Linux 2.6 has some support for hot-swap > -- at least > > at the PCI[-X] level, if not memory and possibly CPU as well. It > > requires extensive support though for that type of > "dynamic" flexibility. > > Memory hotswap ? > Sounds fishy to me, at least on IA32{,e} platforms. Are you > sure about that ? > > []s > > - -- > Rodrigo Barbosa <rodrigob(a)suespammers.org> "Quid quid Latine > dictum sit, altum viditur" > "Be excellent to each other ..." - Bill & Ted (Wyld Stallyns) > > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.4.0 (GNU/Linux) > > iD8DBQFCwuS4pdyWzQ5b5ckRAjSTAJ9hXlQ3kT4JAjSkkn/4QmYrKTFfcwCgkcPv > hsj3g/oh3Fy68DZmGXCygAI= > =y7II > -----END PGP SIGNATURE----- > _______________________________________________ > CentOS mailing list > CentOS(a)centos.org > http://lists.centos.org/mailman/listinfo/centos > > -- > This message has been scanned for viruses and dangerous > content by MailScanner, and is believed to be clean. > > -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.

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Re: Offtopic Posts [was Re: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing]
by Bryan J. Smith <b.j.smith＠ieee.org> 29 Jun '05

29 Jun '05

From: Chris Mauritz <chrism(a)imntv.com> > I agree completely. Unfortunately, even though I've killfiled the > biggest offender, I'm still getting a lot of the noise since people > continue to feed him. I assume the former is a reference to me. As far as the latter, you might re-think your singularity focus. As I've said before, you can't complain about me without complaining about others too. I.e., I try to point out things with_out_ going down into the tangent. Then people "get smart" with me believing what I say is not true. I can then either "let it go" and then people dismiss my offering of my experience and knowledge. Or I can correct them with the tangent. It's a catch-22 for all of us. > If people want to feed the trolls, please, for the love of all that's > holy, trim your posts. 8-) The funniest thing is that when people define what a "troll" is, they aren't just defining it for myself. Your partiality has been noted. ;-> > Sigh, this is the first technical list filter I've ever had to > implement (for email...usenet is another story). No offense but sometimes the "popular" thought or ignorance is worse than the so-called "distractive" discussion that sheds some light on it. People are building servers with CentOS. This stuff is pertinent. I do _not_ introduce it myself, but when it comes up, I _will_ offer my recommendations based on experience and background. If you see people only as "feeding" my so-called "trollish nature," then maybe that's a sign you're not looking at the real issue. I'm not innocent, and I'll _never_ claim to be. But some others are very guilty of wanting many tangents and are posting just as much as I in a thread! Think about it. ;-> -- Bryan J. Smith mailto:b.j.smith@ieee.org

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RE: [CentOS] Postfix / Postini question
by Marc Powell 29 Jun '05

29 Jun '05

> -----Original Message----- > From: centos-bounces(a)centos.org [mailto:centos-bounces@centos.org] On > Behalf Of Barry Brimer > Sent: Wednesday, June 29, 2005 9:47 AM > To: centos(a)centos.org > Subject: [CentOS] Postfix / Postini question > > > > I have a mail server that handles several domains. One of these domains > has > decided to use Postini. For those not familiar with Postini, you set your > MX > records to use their mail servers. They filter mail, and deliver you only > the > clean virus/spam free mail. The idea is to only allow incoming mail from > their > mail servers so spammers are unable to send to your mail server directly. > This > is fairly simple to do with standard restriction classes for a dedicated > mail > server. I am not sure how to accomplish this on a shared mail server. > Ideally > I would like to instruct postfix to accept mail from anywhere for all > domains > except one domain (the one using Postini) and only allow mail destined for > that > specific domain to originate from Postini's mail servers. Any ideas would > be > greatly appreciated. I'm not a postfix guru but I don't believe that is possible with a shared server. However, it's been my experience that if your server is not listed as an MX (and it won't), MXs exist (and they will -- Postini's) then mail will not be delivered to your machine by anyone except Postini. The only two scenarios I am aware of in which mail would get delivered to your server instead of Postini's would be if a) you were listed as a fallback MX or b) no MX's were specified then the A record for your domain would be used. Have you looked through the postfix wiki, documentation, faq, mailing list, etc? That'd be the first place I'd go since they _are_ the postfix experts ;). -- Marc

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RE: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0-> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 29 Jun '05

29 Jun '05

From: Robert Hanson <roberth(a)abbacomm.net> > or should i be more specific with the question(s)? > the reason i ask is that i just dumped 2 gig dram in a basic > P4 Intel 3.0GHz box to play with. > regards and TIA, At more than 1GiB on Linux/x86, you must use a 4G+4G kernel (this is the default) to see more than 960MiB. This causes a signficant (10%+) performance hit. On more than 4GiB, it is worsened as more extensive paging is used. If you have 1GiB or less, you should rebuild with_out_ "HIGHMEM" support which is a 1G+3G kernel, and you'll see better performance (and memory will be limited to 960MiB). In a nutshell, you should be running Linux/x86-64 on systems with more than 1GiB for optimal performance. If you have more than 4GiB of combined system and memory mapped I/O, you should be running Opterons with I/O MMUs. Intel EM64T systems will have protections in place for both earlier generation GTL+ limitations, as well as lack of an I/O MMU. Much of the additional "tangent" surrounded the fact that there are a few so-called "32-bit" Athlons that actually have a BIOS hack and Linux kernel support so it doesn't take a performance hit. Long story short, it has to do with the fact that even so-called "32-bit" Athlons have a core and underlying interconnect platform that supports 40-bit _linear_ addressing _natively_. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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with CentOS 4, and certain RAM, what specific kernel then?
by Robert Hanson 29 Jun '05

29 Jun '05

greetings how about some more of that practical CentOS stuff like amount of RAM vrs specific kernel info... im sure it is in a doc somewhere yet can someone enlighten... in all cases running latest" CentOS 4.... and since we all know when we have more than one processor, it is easy to choose SMP or not... and most of us can tell if we are i386, i586, i686, AMD whatever, Opteron etc... ...yet, what "kernel type" is best at what memory sizes... i know there are standard kernel and "hugemem" kernels and SMP and what have you.... are there others ive missed? at what amount of RAM should we go hugemem? is there more than one amount depending on processor? im guessing yes. is that what a lot of the discussions are about lately? do you always use a stock kernel below that? will a hugemem kernel self destruct at RAM memory amounts lower than what amount of RAM specifically calls for "hugemem"... and again... may i ask what web document spells this all out? regards and tia - rh

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Re: Offtopic Posts [was Re: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing]
by Bryan J. Smith <b.j.smith＠ieee.org> 29 Jun '05

29 Jun '05

From: Greg Knaddison <greg.knaddison(a)gmail.com> > Look - brevity is the soul of wit. It also keeps other folks on lists > from calling you a troll. The problem is that then the same people then start complaining about my "oversimplification." In fact, that's part of the problem here. I really _tried_ to make a recommendation without breaking down into the engineering non-sense. I really don't see how much "wit" I could do to satisify some people on that thread. > You pretty much get to blab as much as you want and argue with > people over tangent issues proving you are right, Dude, at this point, I'm tired of having my experience cut, sliced and diced by people who are like, "WTF does he think he is?" So you're right, I'm going to just state something _once_ and if people don't want to believe it, I'm just going to leave it. I tried several times in that thread, but yes, you are correct, I didn't stop, and I kept posting too. My apologies. > or you get to maintain "non-troll" status. Pick one, but don't > tangentially blab and get upset about being called a tangential > blabber. I don't have a problem with being called a "tangential blabber." What *I* have a problem is being singled out. Dude, re-read back in that last thread. Although I didn't stop posting, at some point, I realized it was going to have to go _deep_ before it would end. Now I've said my peace for the last time. I promise I will not repeat something more than once -- at the most, making only a 2nd post to "clarify" and if I didn't do a "good enough job" by then, I'll leave it be _regardless_. Your opinion is noted. But also note that someone else insinuated there was only *1* troll. I like holding everyone to the same standard. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 29 Jun '05

29 Jun '05

From: Steven Vishoot <sir_funzone(a)yahoo.com> > As Carol Brady said "what was all that about" I dont > know if anyone else feels this way, but i think this > subjuct has been beaten to death and beyond. Not sure > if i remember right, but wasnt the original post about > upgrading from 4.0 to 4.1? How did this topic become > an engineering course? sorry for being a crab...but > come on.... If you deploy servers with more than 1GB of RAM, and definitely more than 4GB of RAM, you should be aware of what limitations there are with Intel solutions. That's what this was about. If someone else wanted to make it into a discussion of board traces and other, irrelevant non-sense, then I'm sorry for getting into that with him. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 29 Jun '05

29 Jun '05

From: alex(a)milivojevic.org > Well, this is how I interpreted Bryan's emails. He'll probably correct me if > I'm wrong (yeah, I have EE, but haven't done much EE work since I > graduated, it just happened to be mostly "software" things for me, so I'm > rather rusty here :-( If you haven't noticed, I am _not_ big on "credentials." As far as I'm concerned, as long as someone has the knowledge, I could care less about the paper**. Even most state BoPEs will allow you to replace an ABET Accredited BSE with 8-12 years of experience (plus another 4-5 years experience post-degree) to qualify to become a PE. There are semiconductor engineering mindsets and they create differ from programmer or even technologist. [ **NOTE: Being a consultant, I finally had to "give in" to the paper. I also decided to major in engineering "just in case I needed it" (and, later on, got to use it for 2 years in the semiconductor industry). ] > I don't think Bryan is talking about "external" width of the address bus, > how many lines you see printed on the motherboard. That's because it is _irrelevant_ in many cases. You can mux lines, which is exactly what the original EV6 Crossbar Athlon does. > He's talking how the things are organized internally, and about the way > the bus logic works. That would be what theoretically implementations > might use, not what some specific implementation is limiting itself to. Exactly. Until the new 40-bit Xeon MPs came out, they were pretty much "slap on" designs with extended ALUs and microcoding to be x86-64 compatible to a point. > Sorry for mixing software and hardware from now on, It hard not to. First you have to consider the programmer aspects. Then you have to realize those will influence hardware compatibility. Then you have to remember that with every new addressing model, you _exponentially_ increase the external logic to drive it. > just trying to make Peter see where his misconception is (the best > way I can, which might not be good way at all). It's fairly difficult to do it without breakout a basic memory controller circuit at least the transistor level, or possibly the combinational NAND gates it somewhat represents. > The programming model for 32-bit userland applications is obviusly > limited to 32 bits -- the sizeof(void *) will tell you that. So single > process can see only 32-bit logical linear address space. To a point. PAE36 is what allows you to break that, because even in the i386, the 16-bit segment register that is offset 4-bits from the 32-bit offset register results in a 36-bit "normalized" address (it can actually be 37-bit, but that's another story). How the processor handles that in a way that is compatible with the OS is the problem. PAE36 uses "paging" from above 32-bit (up to 36-bit/64GiB) down to below 32-bit (upto 4GiB). PAE36 processors can support this paging, and then have at least 36-bit traces on the platform. GTL+ logic was designed with this "slapped on," and never bothered with direct, linear access until just recently (with the new 40-bit redesign for Xeon MP). Athlon, on the other hand, has always been 40-bit EV6. AMD decided to support the PAE36 paging, which added logic. But they _always_ had the "40-bit linear addressing for free" inherently in the platform. That's where these few BIOS hacks come in, combined with an OS/model that can take advantage of it. If you enable this mode for Windows, it will _not_ work! > On the other hand, processor (the hardware) doesn't need to have > such limits, if it's internal organization is wider. So, AMD (processor) > is able to see 40-bit linear physical address space as one single big > chunk of memory. 32-bit applications will have their > 32-bit *logical* address space mapped into this 40-bit linear *physical* > address space of processor. I don't know if programming model of > "32-bit" AMD processors allows you to have wider-then-32-bit pointers > (even if it did, you would have to have compiler that can generate such > code, gcc can't do it for sure). Not true. The model is _still_ PAE36, up to 36-bit/64GiB. But instead of paging, the combination of Athlon's "inherent 40-bit" with an OS that can do it will not use paging. Normally PAE36 does paging, which is what PAE36 OSes normally do. > Obviously, the kernel needs to know how to manage things in this > wider physical address space, the reason why you need patched Linux > kernel to take advantage of it. The actual amount of space doesn't change -- at least not under the PAE36 model. It's just how the OS commands the memory logic to use it, and that also requires the firmware (BIOS) to pre-configure it at POST. Under a norminal PAE36 OS and board, the memory logic and OS always do paging to access above 32-bit/4GiB. But I don't think this hack is able to linearly address the entire 40-bit because of the limitations of what PAE36 can address. > Intel (the processor) on the other hand, is able to physically address > only 32-bit address space. Anything wider than that, it needs to page. > Dealing with paging will obviosly be additional work for OS, hence > lower performance. Paging is a significant hit. Anyone running in the 4G+4G "HIGHMEM" model of their Linux kernel and recompiles for 1G+3G model will notice a noticeable performance gain (as long with only 960MiB of memory). > So while both processors will have more that 32 address lines on the > packaging (and printed on motherboard) minus couple of lowest one > that are not needed) as you can see in various specifications that you > queted, that doesn't mean processor's core actually sees all that > address space. > How else to try explaining this... Hm... Remeber Intel 8086? It could > address only 16-bit address space, but it had more than 16 address lines > on the packaging. It used segmenting (hopefully the right term) to see > wider-than-16-bit address space. Now try to make analogy with what was > discussed so far ;-) It's somewhat correct, although it gets interesting. It's more like EMS than XMS, because XMS used to shunt the processor in and out of Protected286/386, and that required a 286/386 to access it. You could run a true 24-bit/32-bit, respectively, to avoid that. EMS worked on old 8088/8086 (as well as 80286/386), because pages above 1MB could be mapped in. The 80386 and some 80286 could emulate this as well without a special card with special addressing. In the GTL+ bus, this is exactly what it does. It offers special addressing lines for a memory logic that pages, because that's all the OS does. Even the early EM64T processors had to deal with this "limitation" of GTL+ platform. You want to ensure you get a new EM64T platform that doesn't have that approach. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 29 Jun '05

29 Jun '05

From: Peter Arremann <loony(a)loonybin.org> > And that's exactly the part I don't get - if you have a 32bit address model > then you have to use PAE of some sort (compatible to Intel PAE36 or not) to > get to address more than that memory... The BIOS hack basically says "don't be stupid" >4GB. It tells the Athlon MP to the PAE36 addresses linearlly, instead of paging in GTL compatible fashion. With that said, do you mean _beyond_ 36-bit/64GiB? First off, I don't think there ever was an Athlon MP mainboard with more than 64GiB (or more than 32GiB for that matter). Secondly, programs are written to PAE36, so they can only address 64GiB (if not 32-bit/4GiB). *BUT* is it possible for the Athlon MP to still address more than 64GB and "window" (not page) PAE36/64GiB programs? That's a good question, and it's the #1 reason I'm trying to find that post in the LKML. In reality, if the hack uses Linux/x86-64, it could very well be that it puts the Athlon MP in "48-bit/256TiB Long Mode" and translates addreses linearlly. The Athlon MP wouldn't offer PAE52, no. But it _could_ offer PAE36 windows in a 48-bit (40-bit physical EV6) space. Remember, the Athlon/MP and Athlon64/Opteron are the _exact_same_ core design, including the 40-bit/1TiB EV6 interconnect for addressing outside the chip (even if the latter tunnels over HyperTransport between CPUs and I/O to other memory, instead of using a "crossbar switch"). > again - how do I generate a >32bit address when using a 32bit > address model without pages? :-) Remember, in i386 (and, subsequently, the i486 TLB), the segment register is offset at bit 20. That means the most significant bit (MSB) of the segment register actually has a value of 2^35 (32GiB)! Segment: 1111 1111 1111 1111 ____ ____ ____ ____ ____ Offset: ____ 1111 1111 1111 1111 1111 1111 1111 1111 Before PAE36 in the i686, Intel would thrown an exception if you set _any_ of the top 4-bits of the segment register, or if the 5th MSB of the segment was set and either the MSB of the offset, or the previous bits "overflowed" when "normalized" into the physical address. That would result in a physical address >32-bit/>4GiB. In i686 with PAE36, Intel now uses those >32-bit/>4GiB addresses as "pages" into <32-bit/<4GiB addresses. In EV6 with the incompatible "BIOS hack" and a supporting kernel, the Athlon MP's TLB doesn't page, it allows _direct_, _linear_ access above 32-bit/4GiB. Digital EV6 is capable of physically addresssing 40-bit. Intel GTL is only capable of 32-bit. When Athlon is in GTL compatibility mode, it only does 32-bit for full compatibility. But you can tell it to use native, 40-bit EV6 with this BIOS hack. The BIOS hack sets up the crossbar registers which the OS must then support. I'll confirm how this is being done. I believe it actually leverages the Linux/x86-64 kernel. > Once I have that address, throwing it out on the bus is > easy - but how do you generate that address without a PAE? That's where the hack comes in. Remember, _all_ kernels in _all_ OSes use the TLB, hence why an i486 ISA compatible is virtually required these days (or they do it in the kernel's software). Normally the Athlon TLB will do the same thing as any Intel GTL, so any such i686 kernel with PAE36 will normally do the same thing. But the BIOS hack puts the Athlon TLB into its _true_ 40-bit EV6 addressing, and the kernel then knows of this and uses it. > So you're simply talking about being the ability to output an > address longer than 32bit on the bus? It's more than just that. It's the combination of presenting PAE36 to _user_ software, while using _linear_ addressing physically. Intel i686+GTL already does PAE36, and pages in addressings above 32-bit. Athlon+EV6 normally just emulates that, right down to the TLB. This hack doesn't, it unleashes the Athlon as it's meant to work on a 40-bit interconnect designed for 64-bit Alpha processors. And that includes having the kernel drive the TLB to just take those >32-bit "normalized" addresses that would normally be "paged" and just act like it's linear space. As far as above 36-bit, I'm not sure. I'll check on that. > on AMD64, yes, thats for sure... but you were referring to > 32bit athlons in the statement I'm trying to understand. And what I'm saying is that Athlon is Athlon. It's the same core, same 40-bit EV6 interconnect. Everything else is compatibility. On Athlon 64, you can run a PAE52 kernel (on its 40-bit physical platform) and run PAE36 applications, giving linear address space to them all while they think paging is being used. What this hack does is do the same thing for Athlon MP -- marketed as "32-bit," but the _same_ 40-bit capable, _physical_ platform. EV6 is EV6, designed for 64-bit Alpha, and AMD couldn't "cripple" it. They use the same board logic and cores, whether a 32-bit Athlon or 64-bit Alpha are used. But doing anything but traditional, GTL 32-bit/PAE36 would normally _break_ hardware and OSes. Unless you have a hack to the BIOS which enables this "Linux" memory mode, and a kernel which supports it. Again, I'll find the post, which will lead me to the tech info. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: [CentOS] Directory Server for CentOS 4.1
by Bryan J. Smith <b.j.smith＠ieee.org> 28 Jun '05

28 Jun '05

From: Johnny Hughes <mailing-lists(a)hughesjr.com> > The plan for Directory Server for CentOS-4 is to port RedHat Directory > Server (and not Fedora Directory Server) when it is released for RHEL. > That should happen when RedHat thinks it is stable for production in the > enterprise ... I would assume that they will charge for it like they do > for RHGFS/RHCS when they feel they have it stable. I thought that have been doing that since the AOL deal last year? It had been available on the RHN for awhile, in the unchanged/original form. Unless I was mistaken, the deal was that AOL would allow Red Hat to GPL it after an undisclosed number of sales had occurred _or_ by April 30, 2005, whichever came first. The new FDS and RHDS releases are just more updated/integrated releases with the Red Hat product line. E.g., more integrated SASL/Kerberos integration with Red Hat's offerings out-of-the-box. Previously there was a lot of post-install work to get Kerberos working via GSSAPI. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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[OT] CentOS web form troubles
by Paul Heinlein 28 Jun '05

28 Jun '05

It looks as if the "Contact Us" form for sending comments to the CentOS webmasters (http://www.centos.org/modules/contact/) is trying to send mail to donavan(a)mail.centos.org, which apparently gets forward to an account @4wx.net. The mail server for that domain is having a hard time communicating with mail.centos.org. Is there anyone on this list who can confirm, deny, or report the problem? :-) -- Paul Heinlein <> heinlein(a)madboa.com <> www.madboa.com

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Re: [CentOS] U320 PCI-X SCSI HBA experiences on x86_64
by Bryan J. Smith <b.j.smith＠ieee.org> 28 Jun '05

28 Jun '05

From: Alan Hodgson <ahodgson(a)simkin.ca> > Does anyone have any good or bad driver/performance/stability > experiences with either: > LSI Logic LSIU320 > Adaptec 29320ALP-R or (or other current boards using the same driver) > in Opteron servers running RHEL 4 or CentOS 4, x86_64? > Thanks in advance. I can't remember if I brought it up on this list, but my permanent home is less than 5 miles from Adaptec's major support center in Orlando. I know several gentlemen who have worked their throughout the years, and many of them have told me the same thing. If you use Adaptec, use the _retail_ products. The OEM editions have custom firmware and changes, and the Linux drivers are often not guaranteed to work. Indeed I have regularly run into numerous issues with many Adaptec products that have come with servers, even a few of the tier-1 OEMs who ship and support Linux for servers (this is less commonplace in more recent years). As such, I have always preferred Symbios Logic / LSI Logic products because the overwhelming majority of their products are the same -- either retail or whitebox OEM. I've yet to have an issue with the former Symbios Logic 53c8xx/1xxx products or LSI solutions under Linux. If you have an OEM or integrator providing you solutions, especially if you have a SLA with them, then by all means, use what they will support. Otherwise I tend to prefer Symbios/LSI products. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Directory Server for CentOS 4.1
by User Lists 28 Jun '05

28 Jun '05

Hi all, Somebody has tested directory server (http://directory.fedora.redhat.com/wiki/Main_Page) under CentOS 4.1?? Is it ready for production environments?? Somebody has ported to centos?? Thank you very much. __________________________________________________ Correo Yahoo! Espacio para todos tus mensajes, antivirus y antispam ¡gratis! Regístrate ya - http://correo.espanol.yahoo.com/

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U320 PCI-X SCSI HBA experiences on x86_64
by Alan Hodgson 28 Jun '05

28 Jun '05

Does anyone have any good or bad driver/performance/stability experiences with either: LSI Logic LSIU320 Adaptec 29320ALP-R or (or other current boards using the same driver) in Opteron servers running RHEL 4 or CentOS 4, x86_64? Thanks in advance. -- Inside every older person is a younger person wondering what happened

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Web Proxy/Monitoring Software?
by Scott Sharkey 28 Jun '05

28 Jun '05

Hi All, I have a need for a service or software that will monitor and track outbound HTTP (web) accesses, and report what pages are being visited. I know that Squid theoretically can do this, but it seems like overkill for this application. The user could care less about caching - they just want to monitor what URL's their staff is visiting. IS squid the best option, or is there something else that would do a better job? Part of my concern is that the machine they have to run this on does not have a huge amount of memory, and I understand Squid can be a memory hog. Thanks!!! -Scott

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Re: [CentOS] Re: Directory Server for CentOS 4.1
by Bryan J. Smith <b.j.smith＠ieee.org> 28 Jun '05

28 Jun '05

From: Avtar Gill <avtargill(a)gmail.com> > I can't comment about that directory server but I have been using Novell > eDirectory on CentOS 3.* without any problems. Considering that it's > utilized in numerous universities and government organizations around > the world, I would say it's definitely production grade software. Just know that I've seen NsDS deployed in 10,000+ node networks going back to the late '90s. I don't think people realize what deal the community has gotten thanx to yet another Red Hat purchase released, as always, 100% GPL. OpenLDAP wasn't cutting it IMHO, and Red Hat refuses to offer solutions that aren't GPL. Hence why they came to an arrangement with AOL to see NsDS GPL'd after they "gave up" on OpenLDAP. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: [CentOS] Directory Server for CentOS 4.1
by Bryan J. Smith <b.j.smith＠ieee.org> 28 Jun '05

28 Jun '05

From: User Lists <clopmz(a)yahoo.com> > Hi all, > Somebody has tested directory server > (http://directory.fedora.redhat.com/wiki/Main_Page) > under CentOS 4.1?? Is it ready for production > environments?? Somebody has ported to centos?? You _do_ understand it's basically Netscape Directory Server, correct? NsDS has been more "production ready" than OpenLDAP ever has IMHO. And yes, it runs on even non-Linux platforms (e.g., Solaris), so I'd say it runs on just about any Linux platform. Integration considerations might be another, more involved detail though. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: sendmail and spamassassin
by James B. Byrne 28 Jun '05

28 Jun '05

Thanks for all of the advice. I was afraid that I would have to add some sort of glue application to tie the two together. We run MailScanner with Sendmail, DCC, Razor and SA on the final delivery machines but I was hoping to have a frontend filter with a somewhat simpler setup from a maintenance point of view. I have installed amavisd (from Dag Wieers repo.) on one of our MX machines for testing purposes and if, as I anticipate, I have further questions then I will be back. Actually, I have one. The setup documentation refers to a duel sendmail setup. Will the default install work with one sendmail instance? If I have to set up two then I might as well go the whole MailScaner route. Regards, Jim -- *** e-mail is NOT a secure channel *** James B. Byrne mailto:ByrneJB.<token>@Harte-Lyne.ca Harte & Lyne Limited http://www.harte-lyne.ca 9 Brockley Drive vox: +1 905 561 1241 Hamilton, Ontario fax: +1 905 561 0757 Canada L8E 3CE delivery <token> = hal

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Unable to find drives - Centos 4
by Jon 28 Jun '05

28 Jun '05

Installing the Centos 4 release onto a supermicro server with the Adaptec 2015S card (channel 0) but unable to find the hard drives even after loading the Adaptec 79** series driver? Centos 3 loads without issues. Has anyone had similar problems? regards Jon ___________________________________________________________ Yahoo! Messenger - NEW crystal clear PC to PC calling worldwide with voicemail http://uk.messenger.yahoo.com

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sendmail and spamassassin
by James B. Byrne 28 Jun '05

28 Jun '05

I have a problem getting spamd and sendmail (both stock CentOS4 rpms) to work together on a couple of smtp relay machines. This is clearly a configuration issue and no doubt revolves around my lack of comprehension of how this is to work. Basically, the setup consists of two frontend public smtp transports that redirect all email through a firewall to an internal imap server for final delivery. The firewall and sendmail access map prohibit connections to the imap server except for the local MX gateway. The external MX gateway is a fallback mx server that routes everything it queues through the primary gateway. So: MX 2 routes to MX 1 that routes to IMAP MX 2 and MX 1 are running spamd. the sendmail.m4 file has the following at its very end: dnl # dnl # MAILERs are always last after all FEATURES are defined MAILER(smtp)dnl MAILER(procmail)dnl The contents of /etc/procmailrc are: :0fw | /usr/bin/spamassassin Spamd is running on both. There is a local configuration rule set in /etc/mail/spamassassin/local.cf Passing a test message through spamc on MX 1 or MX 2 does not seem to pick up this rule even for messages constructed to trigger it. Passing spam messages through spamc -R identifies messages that have passed through the relays without any spam tags as being high scoring spam. What am I doing wrong? Regards, Jim -- *** e-mail is NOT a secure channel *** James B. Byrne mailto:ByrneJB.<token>@Harte-Lyne.ca Harte & Lyne Limited http://www.harte-lyne.ca 9 Brockley Drive vox: +1 905 561 1241 Hamilton, Ontario fax: +1 905 561 0757 Canada L8E 3CE delivery <token> = hal

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Adaptec Host Raid
by Sugianto Yonatha 28 Jun '05

28 Jun '05

Hi All, I need to install CentOS 4.0 x86_64 using Adaptec ASC-29320A with HostRAID enabled, but it seems my card isn't recognized. I've tried to install the hardware using driver downloaded for RHEL 4.0 from the Adaptec Website, but still it's unrecognized. P.S. I'm able to install RedHat 9.0 using this card before. Is there anyone have any solution for this? Thanks and Regards, Sugianto Y.

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Screaming Interrupt error and hang.
by Lamar Owen 27 Jun '05

27 Jun '05

One system I have is configured thusly: AMD Duron 1200 (I have frequency restrictions in this application, and must stay below 1.3GHz or must be above 2.0GHz, and the 1200 fits nicely in our interference plan; besides, I was given the chip, and it's fast enough for the application). Soyo DRAGON KT400 motherboard, 512MB DDR RAM (DDR266). Silicon Image SATA interface card. Machine boots CentOSPlus 4.1 kernel (2.6.9-11.106.unsupported) perfectly fine UNTIL I plug in a Maxtor SATA drive into the drive slide I have in the machine. Drive and slide work perfectly fine at home with a Gigabyte KT600-based motherboard with VIA SATA interface. After plugging in the SATA drive and rebooting (since libata doesn't yet do hotplug), I get a hang after seeing an 'irq 10: nobody cared! (screaming interrupt?)' error. I have done the kernel command line 'pci=biosirq' and 'acpi=off' suggestions, I have disabled USB, disabled everything that the BIOS will allow. Nothing at this point is sharing IRQ 10 with the Sil 3112 controller. I think it is the latest BIOS version for that motherboard. No matter what I do, it issues the screaming interrupt error until I remove the SATA drive. The DRAGON motherboard has HPT372 software RAID on board (I'm using it as just another two channel ATA host adapter) as well as audio, network, etc). LAN is enabled; both COMs and the LPT are disabled, USB is disabled, audio is disabled. And the motherboard works and has worked perfectly fine for months without the SATA drive in the slide (and with all the peripherals enabled!). Red Hat Bugzilla unresponsive; maybe someone here has seen the problem and knows of some other thing I can tweak. Odd that it works fine with the card in with no drive, but plugging the drive in kills it. With the drive not installed, the card still uses the IRQ, still loads its BIOS, and still shows up in dmesg (this produced with a default boot, non-quiet): [snip] ACPI: (supports S0 S1 S4 S5) ACPI wakeup devices: SLPB PCI0 USB0 USB1 USB2 USB6 USB7 USB8 USB9 LAN0 Freeing unused kernel memory: 148k freed SCSI subsystem initialized libata version 1.10 loaded. sata_sil version 0.8 ACPI: PCI interrupt 0000:00:0b.0[A] -> GSI 10 (level, low) -> IRQ 10 ata1: SATA max UDMA/100 cmd 0xE0832080 ctl 0xE083208A bmdma 0xE0832000 irq 10 ata2: SATA max UDMA/100 cmd 0xE08320C0 ctl 0xE08320CA bmdma 0xE0832008 irq 10 ata1: no device found (phy stat 00000000) scsi0 : sata_sil ata2: no device found (phy stat 00000000) scsi1 : sata_sil device-mapper: 4.4.0-ioctl (2005-01-12) initialised: dm(a)uk.sistina.com [snip] It's in the area after the sata_sil driver gets loaded that, when the drive is plugged in, the screaming interrupt occurs, and the system hangs. It DOES detect the drive, though. Oh, and let me head off the obvious thing at the pass: I'm not using any pseudo-RAID features on either the HPT372 or the Sil 3112. Both chips work fine; the Sil 3112 card was in a Windows box previously and has worked with this drive. The HPT372 is working FINE right now as two independent ATA channels. Just looking for some ideas of things to look at (other than 'don't use a FRAID card' 'try another motherboard' and the like; those pseudoanswers will be ignored; please only answer if you have an idea, don't waste bandwidth telling me you don't know, but that SOYO motherboards are junk, etc. Too much of that around here, unfortunately, and it is annoying). -- Lamar Owen Director of Information Technology Pisgah Astronomical Research Institute 1 PARI Drive Rosman, NC 28772 (828)862-5554 www.pari.edu

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SW-RAID on 2 SATA controllers
by Dag Wieers 27 Jun '05

27 Jun '05

Hi, Would it be advisable to use SW-RAID using 2 different SATA controllers. My system happens to have both a VIA VT8237 and SIL3114 SATA controller, and I thought for both performance reason and redundancy using both for a 2 disk RAID1 array would be best. But it's possible that SW-RAID does not like or cannot overcome problems with such a setup or that one of these drivers is known to have issues. Any insight is welcome :) -- dag wieers, dag(a)wieers.com, http://dag.wieers.com/ -- [all I want is a warm bed and a kind word and unlimited power]

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SW-RAID on 2 SATA controllers
by Dag Wieers 27 Jun '05

27 Jun '05

Hi, Would it be advisable to use SW-RAID using 2 different SATA controllers. My system happens to have both a VIA VT8237 and SIL3114 SATA controller, and I thought for both performance reason and redundancy using both for a 2 disk RAID1 array would be best. But it's possible that SW-RAID does not like or cannot overcome problems with such a setup or that one of these drivers is known to have issues. Any insight is welcome :) -- dag wieers, dag(a)wieers.com, http://dag.wieers.com/ -- [all I want is a warm bed and a kind word and unlimited power]

3 2

One Touch Backups for Centos?
by Scott Sharkey 27 Jun '05

27 Jun '05

Hi All, Does anyone have any experience with the external "one touch" backup solutions for CentOS? I'm not expecting the software to work, that would be a miracle. But does anyone know if the hardware is compatible? Recommendations welcome. -Scott

2 2

RE: [CentOS] sendmail and spamassassin
by Marc Powell 27 Jun '05

27 Jun '05

> -----Original Message----- > From: centos-bounces(a)centos.org [mailto:centos-bounces@centos.org] On > Behalf Of James B. Byrne > Sent: Monday, June 27, 2005 11:56 AM > To: centos(a)centos.org > Subject: [CentOS] sendmail and spamassassin > > I have a problem getting spamd and sendmail (both stock CentOS4 rpms) > to work together on a couple of smtp relay machines. This is clearly > a configuration issue and no doubt revolves around my lack of > comprehension of how this is to work. > > Basically, the setup consists of two frontend public smtp transports > that redirect all email through a firewall to an internal imap server > for final delivery. The firewall and sendmail access map prohibit > connections to the imap server except for the local MX gateway. The > external MX gateway is a fallback mx server that routes everything it > queues through the primary gateway. > > So: > > MX 2 routes to MX 1 that routes to IMAP > > MX 2 and MX 1 are running spamd. > > the sendmail.m4 file has the following at its very end: > > dnl # > dnl # MAILERs are always last after all FEATURES are defined > MAILER(smtp)dnl > MAILER(procmail)dnl > > > The contents of /etc/procmailrc are: > > :0fw > | /usr/bin/spamassassin > > > Spamd is running on both. > > There is a local configuration rule set in > /etc/mail/spamassassin/local.cf > > Passing a test message through spamc on MX 1 or MX 2 does not seem to > pick up this rule even for messages constructed to trigger it. > Passing spam messages through spamc -R identifies messages that have > passed through the relays without any spam tags as being high scoring > spam. > > What am I doing wrong? Regardless of your test, your biggest problem is that procmail isn't, and won't, be run on your MX machines because they are not doing local delivery to the mailboxes as I understand your setup. Procmail only comes into play when the messages are being put into the user's mailboxes. You'll want to look at something like MailScanner if you want to do all your spam/virus filtering on your MX servers since that works directly with the queue files and re-injects them back into an outgoing queue for final delivery. There are some drawbacks to that, primarily being that you can't have per-user variation, but we did it quite successfully for several years for ~37,000 users with the same type of architecture you are trying to implement. We have since moved to using MailScanner on our MXs for virus checks, attachment stripping and general mal-ware removal only and our local delivery machines run spamd as a postfix filter so that we can have per-user spam settings. There are quite a few how-tos out there to help you, starting with the spamassassin wiki. -- Marc

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RE: [CentOS] Server Crashing
by Ash Christopher 27 Jun '05

27 Jun '05

You could try the following instead of memtest86, since it has numerous limitations. http://people.redhat.com/dledford/memtest.html Memtest86 didn't report any problems on my server, but this script was able to find them. -----Original Message----- From: centos-bounces(a)centos.org [mailto:centos-bounces@centos.org] On Behalf Of Greg Knaddison Sent: Monday, June 27, 2005 10:01 AM To: CentOS mailing list Subject: Re: [CentOS] Server Crashing On 6/27/05, Jay <jaybeattie(a)gmail.com> wrote: > On reboot all is fine. > It's running apache and DNS no SSH access. It passes memory test Memtest86. > How long did you run Memtest86? My understanding is that you can run it and have it work for a couple of hours, but then have it fail after two or three days running. Greg _______________________________________________ CentOS mailing list CentOS(a)centos.org http://lists.centos.org/mailman/listinfo/centos

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Server Crashing
by Jay 27 Jun '05

27 Jun '05

Greetings. Every couple of day's I have a web server running CentOS 4.1 with all the patches as of Saturday that is crashing every couple of day's. Usualy between 4-6 am. The Console shows: Double Fault gdt at xxxx memory Double Falut tss at xxxx memory On reboot all is fine. It's running apache and DNS no SSH access. It passes memory test Memtest86. I can provide more information if you direct me on what to send. Thanks -Jay

4 3

mythtv on centos4
by Tony 27 Jun '05

27 Jun '05

Has anyone had any success or failures with installing mythtv onto centos4? Even better, has anyone any prebuilt rpms to do this? Looks to me like centos+mythtv is quite an interesting prospect in the always-on single home server environment. -- Cheers, Tony

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Re: CentOS 4.0 -> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 27 Jun '05

27 Jun '05

From: Johnny Hughes <mailing-lists(a)hughesjr.com> > That is by design ... the i686 glibc will not work with the c3 ... the > i686 kernel will. Interesting. Hmmm. > You need to use the i386 glibc. As written, the latest RH glibc SRPM > will not build for --target i486 or --target i586 ... But I've seen several packages where building for --target i386 still results in an --march=i486. In fact, that's probably why they clearly still say ".i386.rpm" despite requiring i486 ISA. > I am close to making it build properly for --target i586, but since > the .i386 glibc works well on i586 and it should build with that > target unmodified in the future, that is the way we will proceed. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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RE: [CentOS] Multiple system updates
by Bryan J. Smith 27 Jun '05

27 Jun '05

From: Peter Arremann > This is a question for you guys out there that have a bunch of similar > configured systems out there... How do you handle your updates? I do not mean > the technical level, but from the logistics. No updates? Just run yum by cron > and grab the latest of the web and trust the developers that it works? > Deploy only certain packages automatically (i.e. omit kernel updates)? > run your own yum/apt/up2date/whatever repos? Unless there are only 2-3 systems, the last option. I _always_ maintain an internal repository that goes through its own "enterprise release." One test system always gets the task of regression testing a new set of updates before it hits production. High security rollouts happen ASAP, other rollouts are far less pressured. For only 2-3 systems, I still have a test system, but it's cheap and its hardware does not match production. So I test on one production as long as I can before upgrading all. If I had a huge client base, I'd just maintain my own repository on the Internet with my releases they feed from. So far, my clients have always had their own resources to maintain the repository and procedures after I setup it up and left.

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CentOS-announce Digest, Vol 4, Issue 11
by centos-announce-request＠centos.org 27 Jun '05

27 Jun '05

Send CentOS-announce mailing list submissions to centos-announce(a)centos.org To subscribe or unsubscribe via the World Wide Web, visit http://lists.centos.org/mailman/listinfo/centos-announce or, via email, send a message with subject or body 'help' to centos-announce-request(a)centos.org You can reach the person managing the list at centos-announce-owner(a)centos.org When replying, please edit your Subject line so it is more specific than "Re: Contents of CentOS-announce digest..." Today's Topics: 1. CentOS-4/alpha 4.1beta is there to play (Pasi Pirhonen) 2. CESA-2005:524 Moderate CentOS 3 i386 freeradius - security update (Tru Huynh) 3. CESA-2005:524 Moderate CentOS 3 x86_64 freeradius - security update (Tru Huynh) ---------------------------------------------------------------------- Message: 1 Date: Sun, 26 Jun 2005 18:32:38 +0300 From: Pasi Pirhonen <upi(a)iki.fi> Subject: [CentOS-announce] CentOS-4/alpha 4.1beta is there to play To: centos-announce(a)centos.org Message-ID: <20050626153238.GM21054(a)core.upi.iki.fi> Content-Type: text/plain; charset="us-ascii" Hi, I've always been kind of on/off with alpha. Remember making some kind of debian/alpha installer back -97ish. Lately (like past 2 years), i've been compiling SRPMS on alpha too from time to time. Most of my alpha hardware was pretty much ancient crap, so i wasn't quite confident pushing anything out to public as i wasn't able to test even if EV6 would be ok. Little over week ago i got a AlphaServer ES45, which was the turning point on this all (i thank you whom gave me this box once again even tho i cannot reveal any names). There is lot to personally thank for AlphaCore project as some of the patches i got directly from that work, would have been nasty for me to spot out. I just don't feel that building FC3 for alpha is enought and will be long term maintainable. That's where CentOS-4/alpha should kick in as the basic codebase should be maintained next 7ish years. There are modified SRPMS beoynd the normal CentOS mods, but it's some 30ish of those now, so it's only really few of them all. AVAILABILITY: http://beta.centos.org/centos/4.1beta/isos/alpha/ - which does have ISO-images and .torrent files for CD/DVD-images. - DVD-image does contain full binaries + source - ISOS labeled 'bin' are binaries only - ISOS labeles 'src' are the sources http://beta.centos.org/centos/4.1beta/os/ - which is unpacked, installable tree. http://beta.centos.org/centos/4.1beta/ - generally as this is the point when the yum config should point for updates etc. BETA RELEASE INFO: It ain't perfect. There are lot to improve still. I just wanted to make this public beta now so there might be some community interest/help for making it really smooth. One thing woth of mentining is that CFLAGS have been '-mtune=ev6' for all the packages, that does obey normal rpmbuild process. I am not sure what the impact is in real life, but IMO it won't make a really slow hardware any _slower_ and might even a little faster for anything useable (no pun intended. 'useable' may vary from person to person :) EXPECTED FINAL RELEASE TIME: I'd expect this to be bit much polished up time of CentOS 4.2 will be reality. At least it's where i am aming for final release. TESTED PLATFORMS: - a quad-1GHz ES45 w/ Radeon 9250 (PCI) - a AlphaStation 255/233 (text mode install) - a AlphaStation 1000 (text mode install) - ES45 was trested with console=ttyS0 too from the DVD KNOWN ISSUES: - The kernel isn't stock same one it's in other CentOS-4 releases - The php was replaced with new one - compat-glibc isn't there yet. Neither the later one or the Compaq release Redhat 7.2 one. I've patched the compat-glibc-2.3.2-95.30axp.src.rpm to build, but it was too late to include it to ISOs as i haven't had much time to test it and there is not real needs for this. - anaconda is putting the 'rhgb quiet' on command line even after text installtion, which might just crash the boot as graphics we're asked for first place. - the DVD isn't working at least on my ES45 with IDE-drive. SCSI is fine. I have to look about mkisofs ordering, because that might just be so that those needed files are 'unreachable' for SRM w/ IDE. - the aboot menu lacks the predefined selection for 'text askmethod' for forced text mode instalaltion from net for example. Forgot that one. - SELinux rulesets aren't quite right for everything, so disabling/making it warn level lets it boot better now on installation. - I've built some of the packages by disabling the checks at buildtime, so there might be 'non-working' software. namely gmp, subversion from memory. INVOLVING: - join the mailing lists at http://lists.centos.org/mailman/listinfo/centos http://lists.centos.org/mailman/listinfo/centos-devel - mail me directly to upi(a)iki.fi - more information from http://www.centos.org/ That's about it. I am sure i've already forgotten much i ment to say on this beta release announcement, but now i do push send and worry things later more. -- Pasi Pirhonen - upi(a)iki.fi - http://iki.fi/upi/

1 0

Multiple system updates
by Peter Arremann 27 Jun '05

27 Jun '05

This is a question for you guys out there that have a bunch of similar configured systems out there... How do you handle your updates? I do not mean the technical level, but from the logistics. No updates? Just run yum by cron and grab the latest of the web and trust the developers that it works? Deploy only certain packages automatically (i.e. omit kernel updates)? run your own yum/apt/up2date/whatever repos? Thanks for your time, Peter.

2 1

RE: [CentOS] OT: question on setting up an email server
by Bruno S. Delbono 27 Jun '05

27 Jun '05

> Don't know if qmailtoaster already has been mentioned. It's really easy to > setup and > I'm really happy with my setup. > > http://www.qmailtoaster.com/ >From postfix-users@ Georgi Guninski have found a remotely-exploitable security hole in qmail. <http://www.guninski.com/where_do_you_want_billg_to_go_today_4.html> D. Bernstein denied the claim, classified it as "portability problem" and refused to pay the prize. <http://cr.yp.to/qmail/guarantee.html> Qmail's ML responded nervously to Guninski's post. Like everytime when anyone dare to say anything negative about qmail... It's quite interesting: "I said that Guninski's dick isn't half as big as he's trying to claim." "Go masturbate somewhere else." "Learn to read, moron." Link - http://tinyurl.com/caooe ----

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strange problem on regconizing /dev/sda and /dev/hda
by Ceg Ryan 27 Jun '05

27 Jun '05

I installed a 4.1 x86_64 with kernel 2.6.9-11.ELsmp (rpm) initially. My box is tyan 5350 and a SATA harddisk The install was successful and the harddisk was detected as /dev/sdaX But strangely, when I first reboot my machine. The harddisk change to /dev/hdaX What is the problem ? Below are some of dmesg output hda: WDC WD1200JD-00HBB0, ATA DISK drive Probing IDE interface ide1... Probing IDE interface ide2... Probing IDE interface ide3... Probing IDE interface ide4... Probing IDE interface ide5... Using cfq io scheduler ide0 at 0x1f0-0x1f7,0x3f6 on irq 14 hda: max request size: 1024KiB hda: 234441648 sectors (120034 MB) w/8192KiB Cache, CHS=16383/255/63 hda: cache flushes supported hda: hda1 hda2 hda3 hda4 < hda5 > ide-floppy driver 0.99.newide usbcore: registered new driver hiddev usbcore: registered new driver usbhid drivers/usb/input/hid-core.c: v2.0:USB HID core driver mice: PS/2 mouse device common for all mice md: md driver 0.90.0 MAX_MD_DEVS=256, MD_SB_DISKS=27 NET: Registered protocol family 2 IP: routing cache hash table of 2048 buckets, 112Kbytes TCP: Hash tables configured (established 524288 bind 37449) Initializing IPsec netlink socket NET: Registered protocol family 1 NET: Registered protocol family 17 ACPI: (supports S0 S1 S5) ACPI wakeup devices: PCE0 PCE1 PCIX PCIB USB1 USB2 USBE KBC0 MSE0 Freeing unused kernel memory: 164k freed SCSI subsystem initialized libata version 1.10 loaded. ata_piix version 1.03 ACPI: PCI interrupt 0000:00:1f.2[A] -> GSI 18 (level, low) -> IRQ 193 ata: 0x1f0 IDE port busy PCI: Setting latency timer of device 0000:00:1f.2 to 64 ata1: SATA max UDMA/133 cmd 0x170 ctl 0x376 bmdma 0x1478 irq 15 ata1: SATA port has no device. scsi0 : ata_piix

2 3

"vsftpd is dead but subsys is locked"
by Draden 26 Jun '05

26 Jun '05

If someone could give advice - I am running Centos 4 and on it I am running among other things vsftpd. Today I noticed the ftp services wasn't running, when I went to restart it it says it starts, but there is no pid for it. when I do a status on it, it gives a message saying "vsftpd is dead but subsys is locked" I have tried removing the lock file and no joy. I even just resorted to a reboot hoping that would clear the issue and to no avail Draden -- "Delivery yesterday, Code today, Think Tomorrow"

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Re: Raidcore SATA support
by Bryan J. Smith <b.j.smith＠ieee.org> 26 Jun '05

26 Jun '05

From: Mark Weaver <mdw1982(a)mdw1982.com> > Hi all, > I was wondering if anyone has tried and succeeded to use this > controller. Its the bc4852 SATA controller. There's supposed to be > support for it, but so far we've not been able to get the driver to load > during the install and thus we've got no "valid drive" on which to load > the OS. Last time I checked, but I could be wrong, Broadcom's RAIDCore solutions are FRAID. They are very, very high-end FRAID designs (PCI-X, 8 channel), with lots of software IP for rebuild options, etc..., but still FRAID. I've never personally tried the cards because they aren't any cheaper than 3Ware solutions. But they claim integration tools with Linux's LVM/MD (I have no idea how these work) and should have at least ATA/SATA channel drivers for just a bunch of disks (JBOD) as with any ATA/SATA controller. Luckily Broadcom's new IC for either PCIe x4 or PCI-X 1.0 is an intelligent, MIPS-based hardware solution for either SATA or new Serial Attached SCSI (SAS). The pricing should be similar with the controller being under $60/1K quantity, but finally bring some serious performance to the table (along with up to 768MB of battery-backed DRAM). -- Bryan J. Smith mailto:b.j.smith@ieee.org

4 4

Getting Mailman Running
by John Hinton 26 Jun '05

26 Jun '05

On a CentOS 4 box, I'm trying to get Mailman running. I found the apache conf file in /etc/httpd/conf.d and set the servername in that. When I try to go there, I get a 500 internal server error.. when I try to start Mailman, I get Starting mailman: Site list is missing: mailman I've never run Mailman before.. looked in the /etc/mailman/sitelist.cfg.. don't see anything in there that needs to be set. man mailman shows no entries..... I installed it via rpm at server install time. I am running sendmail. python is installed... I can't seem to find much to help. Thanks, John Hinton

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Re: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 26 Jun '05

26 Jun '05

From: Peter Arremann <loony(a)loonybin.org> > Then the first AnandTech benchmark article > (http://www.anandtech.com/IT/showdoc.aspx?i=2447) is exactly what you want to > look at. Huge amount of memory (when compared to the size of the database > running on the system) on a 64bit linux kernel... > We're doing the same for one of our apps called IPM. Its a PHP app running > against a quad opteron with 16GB ram. Heavy on network IO (during business > hours its rare that we don't saturate the main 100mbit link) but little disk > activity. DB size is about 2.5GB and we end up with a couple of gig for disk > buffers. CentOS4 of course... anything specific you're looking for? I think I know where you and I are differing. When you talk about "heavy [network] IO," you refer to SQL-based applications over a primary 100mbit link. In reality, the MCH bottleneck isn't much of an issue here. When I talk about "heavy [network] IO," I'm typically referring to less intelligent applications (e.g., NFS or other "raw block" transfer) over one or even multiple GbE, possibly FC-AL links (possibly direct IP, link agregated IP, maybe 1 out-of-band channel, or possibly to a Storage Area Network, SAN). Although I have built financial transaction systems that have required GbE as well as engineering. I guess this is where my terminology really differs. A lot of people are using Linux for Internet services. I've typically been using Linux for high-performance LAN systems -- both "raw block" as well as intelligent applications. My Internet connection is not my bottleneck. BTW, despite popular thought, this can be done quite inexpensively when needed. It really all depends. But in these applications, definitely _not_ going to see Opteron doing much for you over Xeon. Let alone not when running Linux or Windows (Solaris might be another story though). -- Bryan P.S. Just a follow-up, _never_ assume you're the only EE in a thread. [ Let alone don't assume I haven't designed memory controllers as part of my job, beyond just my option in computer architecture. That's why I had to "give up" in the other thread, because everytime I try to explain something, you are going to a very simplified path and I have to stop and explain it (e.g., the fact that IA-32/x86 _can_ address beyond 4GiB). ] -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 25 Jun '05

25 Jun '05

From: Peter Arremann <loony(a)loonybin.org> > Actually apps like the one I was referring to showed about 50% > single thread performance gain when going from a 2.4GHZ Xeon > to a 2.2GHz Opteron. That's not a good comparison because the ALU-Control of the Athlon is about 50% faster MHz for MHz than P4-Xeon. So that could easily be a computational benefit and not an interconnect one. > Never assume you've done more more than others either :-) I didn't. > I've done the more difficult job with finding all the applicable documents Dude, you did _not_ send me any documentation I have not already seen. I have been using developer.intel.com years in my semiconductor design career, as well as more of an IT-level system designer. The problem here is that you can't seem to understand that a trace does _not_ indicate how something actually works in the memory logic. E.g., the existence of trace does not tell you if a normalized address that results in a PAE36 (>4GiB) address is going to either: A) Directly drive that trace and fetch for the process to use B) Be intercepted by the paging logic, referenced in a page table, then _that_ logic actually fetches the memory, which is then mapped into <4GiB for the process to use It's not just the simple trace, and it's not just the simple, programmer-level logic. If Intel PAE36 processors didn't have address lines above bit 31, they couldn't address above 4GiB at all! But just because they have those traces doesn't mean they can directly use them. First you looked at it from the "programmer" level, then you looked at it from the "board technician" level. Now I'm tell you _get_in_the_chip_! > while you just put out hearsay and "doesn't work like that" statements > without really backing it up. And yes, IA-32 _can_ address more than > 4GB - called PAE. Exactly! What I'm telling you is that _all_ Athlon "32-bit" processors can by-pass PAE36, and significantly _increase_ performance at the page table level. But it requres the platform be configured in a way that is _incompatible_ with all OSes _except_ a hack for Linux. This is rare, but it has been done in a few mainboards. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 25 Jun '05

25 Jun '05

From: Peter Arremann <loony(a)loonybin.org> > Then enlighten me - if I have 40 address bits - transmit only the higher 37 > since I don't need the lower end. Timing schemas show only one Input hold > time per address transfer for all available pins - how can that be a 32bit > bus? (ftp://download.intel.com/design/Xeon/datashts/30675401.pdf) Once again, stop assuming a trace and its specifications for board layout means that memory is directly addressable over those pins. We could go on that all night and for days, and I can give you countless examples of embedded, PC and other memory controllers, memory technology, etc... where paging and other "swap" is required. Heck, as an EE, I would ass-u-me you would have been exposed to memory controller design. It is a complex mess whereby each new change in addressing exponentially increases the transistor count. > And, if timing diagrams, pinouts and so on lie about the size of the bus, > ... cut derrogatory non-sense ... *STOP* This is why I can't even begin. I _never_ said that Intel didn't offer 64GiB (36-bit) memory addressing. The traces _must_ exist so Intel can on [A]GTL+ platforms, but it does not mean that there is not some "paging" going on at the memory _logic_. I just said it cannot address it linearly -- directly by 36-bit -- in the GTL design. It all goes back to Intel's belief that IA-64/Itanium would have taken over the i686/GTL world by now when it decide not to build a new architecture for IA-32 back in the '90s. A belief that Intel has not been paying the price for, and quickly retrofiting everything it can ASAP. AMD decided to switch to EV6 instead as its foundation for _all_ current processors back in 1996+, and that includes tunneling EV6 over HyperTransport in Athlon64/HyperTransport. This has to do with the fact that the Athlon core is a true 40-bit addressing processor, and not 32-bit with PAE36 to page in the "overhang" from a segment+offset that is normalized above 4GB. Athlon just _emulates_ PAE36 for compatibility. If you hit "/proc/cpuinfo" on _any_ Athlon, it will show that the PAE36 flag is supported. PAE36 support has _always_ been in _every_ Athlon because the core design is 40-bit EV6. AMD took the time, effort and transistors to emulate PAE36 at the control, and put in the logic in its TLB and memory controller. If they didn't, then AMD wouldn't be able to run any PAE36 OSes or applications. And even if you don't have more than 4GB of RAM, there is still the memory organization issues. E.g., Red Hat currently ships i386/i686 kernels with the 4G+4G model which hurts performance over the 1G+3G model. Why does it hurt performance? Because it either relies on the PAE36 paging logic, or a software emulation of it (if the processor does not support PAE36). With the BIOS hack and kernel, this allows Athlon MP to linearlly address directly above 4GB. Intel is _finally_ just coming out with its first, true 40-bit physical interconnect that breaks the limitations of GTL. People should be wary to _not_ go with the majority of Intel's existing platforms because of this, even those with EM64T. Only these newer platforms. > And if its not, then your whole speach about the pae36 > differences between a gtl+ or ev6 connected device is > wrong, which then in turn makes the only real difference > the iommu the newer athlon cores provide (so dma can go > above the first 4GB rather than having to be bounced)... > This is also supported by the intel, amd and redhat docs > (see links posted above and in previous mails), the post > Feizhou made in this thread convering the LKML references about > using the apggart and even microsoft > (http://www.microsoft.com/whdc/system/platform/server/PAE/pae_os.mspx) I know, I also posted it, and there are even _more_ comments in the LKML. There are comments on how AMD has extra GARTs in the Athlon (yes, even the so-called "32-bit" Athlon) to handle _all_ I/O, not just AGP (long story). But I'm not talking just about that. I'm talking about the serious limitations with GTL itself -- even on Socket-640 and Xeon EM64T. It's only the latest > *shrugs* Intel, AMD and any other spec sheet you can find down > to VIA chipset docs agrees with that... But I guess I'm still > wrong though? Dude, you are using _board_level_ spec sheets. I'm talking about the _internal_ design of the CPU/interconnect and how it handles the addressing between the systems software and interconnect. You get that from _neither_ of the "board level" spec sheets _nor_ the "programmer" guides. You have to find more eccentric docs, many times, they are not on-line. Intel is not going to boast how even their AGTL+ chipsets with first-gen EM64T can't directly address above 4GiB because of legacy design limitations in the platform. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 24 Jun '05

24 Jun '05

From: Peter Arremann <loony(a)loonybin.org> > Thanks - but both links again talk about a 32bit/4GB schema and don't talk at > all about addressing >4GB without the need for paging - that was the > statement Bryan made when posting. Correct. The links to the posts he provided were the _same_ as the the posts at the bottom of my original link. I'm still trying to find the post I was referring to. As I said, apparently it was _not_ in the 2004Feb17 thread on Intel EM64T. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: Opteron Mobo Suggestions -- the follies of typical tape backup (it's the 21st century)
by Bryan J. Smith <b.j.smith＠ieee.org> 24 Jun '05

24 Jun '05

From: Kirk Bocek <t004(a)kbocek.com> > Another poster (sorry, could find the name, was it Peter?) mentioned the > lack of hot-swap support in most of the hardware raid out there. If this > is the case, what's the point of raid 1 or 5 if a failed drive will hang > the system? What's your experience with the 3Ware cards? "Hot-swap" is like saying "3D accelerator," there are different features and, sometimes, if you don't have them all, they don't work. #1 is dealing with transient power #2 is dealing with the hardware ATA disconnect #3 is dealing with the software ATA disconnect While many carriers claim to solve #1 for ATA, _only_ SATA with its staggered data/power (using the 15-pin power, and not the legacy 4-pin Molex) is the _best_ guarantee. But typically #1 is not that much of an issue, because the carrier does a decent job at this (some better than others though). The big issue with "FRAID" is at #2. A biggie is when you use the master/slave and remove one. But even if you do master-only, how do you take out a device and replace it -- virtually "resetting" the ATA-PCI arbitration. It typically does _not_ work if the ATA controllers are directly connected to the system's PCI interconnect. But let's say you get #2 to work, now #3 is the biggie. How to you get the OS to "reload" what it thinks is a fixed ATA channel with a fixed drive. Sometimes the FRAID driver does a _poor_ job of it. This is what I see get people all-the-time. In the case of 3Ware cards, the system _never_ -- let me repeat that -- _never_ sees the ATA channel. The system, including the PCI interconnect, _only_ talks to the on-board ASIC. The ASIC then drives the ATA channels. In FRAID, the system, it's CPU and the PCI bus drive and talk _directly_ to the ATA channels. Intelligent RAID uses its on-board intelligence instead. FRAID doesn't have any. > Okay, okay, you win! You're right and I'm wrong! Dude, this isn't about "right and wrong." It's _never_ about that. It's about my sincerest wish not to see you with downtime. It's one thing for me to argue "good" v. "ideal," take it as you wish. But that's very, very, _very_ different than this. In this case, I'm arguing "proper" v. "risky" system design. But it's your system. > I will never consider IEEE-1394 again. You and the other posters > have convinced me. Every USB cable in my server room will be > removed and destroyed. Every USB port will be filled with glue. :) I don't think we _ever_ said that. We just said don't use IEEE-1394 or USB for removable storage on a server. You can continue to use IEEE-1394 and USB for non-storage devices, including input and media as necessary. GOLDEN RULE: As long as the server doesn't "mount" the IEEE-1394 or USB device, then you're "safe." If it "mounts," then you just put your entire kernel at the mercy of its availability. ;-> > What about LVM snapshots? I've been using these for awhile with no > problems. Yes, I understand that it will consume disk bandwith but > that's not a limitation in my installation. Snapshots are an "on-line" backup and they only work if your filesystem isn't _toast_. They aren't the same as "near-line." Again, read the "document" I sent you off-line. ;-ppp -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Re: [CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 24 Jun '05

24 Jun '05

From: James Olin Oden <james.oden(a)gmail.com> > Any idea what the BIOS actually does to enable "linux" memory mode? > That is what registers are poked in the MCH (I assume it would be the > MCH)? Do you think this could be done post bios by say a boot > loader? It completely _breaks_ Intel GTL compatibility at the APIC level IIRC. You can _not_ run Windows on it or a "normal" Linux kernel. From: Feizhou <feizhou(a)graffiti.net> > http://marc.theaimsgroup.com/?l=linux-kernel&m=107759901509280&w=2 > The Linux option in bios is mentioned here. > http://marc.theaimsgroup.com/?l=linux-kernel&m=107757492125437&w=2 > I think what Bryan here is talking about is called IOMMU by the kernel guys. No, that was already at the bottom of the link I sent before. I was referring to _another_ thread where a gentlemen from AMD (with an amd.com address) was talking about the hack that enables this. It is a little known feature because only 2-3 mainboards have the BIOS hack as an option. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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[OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing
by Bryan J. Smith <b.j.smith＠ieee.org> 24 Jun '05

24 Jun '05

From: Maciej ?enczykowski <maze(a)cela.pl> > That's a good point - does anyone know what the new Intel > Virtualization thingamajig in the new dual core pentium D's is about? It's all speculation at this point. But there are _several_ factors. But I'm sure the first time Intel saw AMD's x86-64/PAE52 presentation, the same thing popped into my mind that popped into Intel's mind ... Virtualization - The 48-bit/256TiB limitation of x86-64 "Long Mode" There is a "progammers limit" of 48-bit/256TiB in x86-64 "Long Mode." This limitation is due to how i386/i486-TLB works -- 16-bit segment, 32-bit off-set. If AMD would have choosen to ignore such compatibility, it would have been near-impossible for 32-bit/PAE36 programs to run under a kernel of a different model. But "Long Mode" was designed so its PAE52 model could run both 32-bit (and PAE36) as well as new 48-bit programs. We'll revisit that in a bit. Now, let's talk about Intel/AMD design lineage. - Intel IA-32 Complete Design Lineage IA-32 Gen 1 (1986): i386, including i486 - Non-superscalar: ALU + optional FPU (std. in 486DX), TLB added in i486 IA-32 Gen 2 (1992): i586, Pentium/MMX (defunct, redesigned in i686) - Superscalar 2+1 ALU+FPU (pipelined) IA-32 Gen 3 (1994): i686, Pentium Pro, II, III, 4 (partial refit) - Superscalar: 2+2 ALU+FPU (pipelined), FPU 1 complex or 2 ADD - P3 = +1 SSE pipe, P4 = +2 SSE pipe Intel hasn't revamped it's aging i686 architecture in almost 12 years. the Pentium Pro through Pentium III are the _exact_same_ 7-issue (2+2+3 ALU+FPU+controll) design (the P3 slaps on one SSE unit), and the Pentium 4 was a quick, 18-month refit of longer pipes (with associated reduction in ALU/FPU performance MHz for MHz) that extended pipes for clock (and added a 2nd SSE unit). I'm sure Intel's reasoning for not bothering with a complete generation redesign beyond i686 is because it thought EPIC/Predication would have taken over by now. The reality has been quite the opposite (which I won't get back into). Since then, Intel has made a number of "hacks" to the i686 architecture. One is HyperThreading which tries to keep its pipes full by using its control units to virtualize two instruction schedulers, registers, etc... In a nutshell, it's a nice way to get "out-of-order and register renaming for almost free." Other than basic coherency checking as necessary in silicon, it "passes the buck" to the OS, leveraging its context switching (and associated overhead) to manage some details. That's why HyperThreading can actually be slower for some applications, because they do not thread, and the added overhead in _software_ results in reduced processing time for the applications. "Yamhill" IA-32e aka "EM64T" was just a P4 ALU refit for x86-64/PAE52, but it lacks many design considerations that the Athlon has -- especially outside the programmer/software considerations, and definitely more at the core interconnect/platform.. I.e., because Intel continues to use a single-point-of-contention "memory controller hub" (MCH), memory interconnect and I/O management, among other details, are still left to the MCH. This is going to become more and more of a headache. The reality is that the Intel IA-32e platform _must_ get past the "northbridge outside the CPU" attitude to compete with AMD. As such, I have _always_ theorized that "Yamhill" is a 2-part project. Part 2 is the first redesign of a x86 core in almost (now) 12 years, which goes beyond merely adding true register renaming and out-of- order execution (which are largely hacks in the P4/HT), but goes directly to the concept of virtualizing cores. More on that in a bit, now AMD ... - AMD x86 Complete Design Lineage AMD Gen 1 (1992*): i386/486 ISA -- 386, 486, 5x86, K5* - Non-superscalar: ALU + optional FPU (std. in K5) AMD Gen 2 (1994*): i486/686 ISA -- Nx586+FPU/K5*, Nx686/K6 - Superscalar: 3+1 ALU+FPU (ALUs pipelined, FPU _not_ piplined) AMD Gen 3 (1999): i686/x86-64 ISA -- Athlon, Athlon64/Opteron - Superscalar: 3+3 ALU+FPU (pipelined), FPU 2 _and_ 1 ADD/MULT - Extensions are microcoded and leverage ALU/FPU as appropriate *NOTE: The NexGen Nx586 released in 1994 forms the basis for latter K5 (i486) and the K6 (i686). AMD had scalability issues with its original non-superscalar K5 design and purchased NexGen. SIDE NOTE: SSE Comparison - P4 can do 3 MULT SSE (1 FPU complex + 2 SSE pipes) - Athlon can do 3 MULT SSE (2 FPU complex + 1 FPU MULT) Contrary to popular opinion, Athlon64/Opteron is the _same_core_ design as the 32-bit Athlon platform. It is still the same, ultra- powerful 3+3 ALU+FPU core, with its 2 complex + 1 ADD/MULT FPU able to equal Intel's 1 complex _or_ 2 ADD FPU plus 2 SSE pipes at doing the majority of matrix transforms (which are MULT -- hence why Intel's FPU can't do 2 simultaneously, and relies heavily on its precision-lacking SSE pipes). Also contrary to popular opinion, 40-bit/1TiB Digital Alpha EV6 interconnect forms the basis for _all_ addressing in _all_ Athlon releases, including the 32-bit. There are a few mainboards that allow even 32-bit Athlons to safely address above 4GB with _no_ paging or issues (with an OS that offers such a supporting kernel, like Linux). The 3-16 point EV6 crossbar and not "hub" architecture, forced Athlon MP to put any I/O coherency login in the chip, so the AGPgart control is actually on the Athlon MP, and not in the northbridge. This has evolved into a full I/O MMU in Athlon64/Opteron. Because Athlon is 5 years newer than Intel i686, and there is a wealthy of talent influx from Digital (even though Intel did get some as well, they haven't redesigned i686 completely), Athlon has some of the latest, run-time register renaming and out-of-order execution control in the core itself. This is why doing something like HyperThreading would benefit AMD _very_little_ and largley introduce self-defeating (and even performance reducing) overhead. In addition to the design of PAE52, the #1 reason why you can safely assume AMD is moving towards virtualization is because of the design limits they put on Athlon64/Opteron. E.g., although the original 32-bit Athlon platform used logic that allowed up to the full EV6 8MB SRAM addressing (cache), Athlon64/Opteron has been artificially limited to 1MB SRAM (saving many considerations and other benefits). This clearly indicates AMD did not consider Athlon64/Opteron - The Evolution to Virtual Cores AMD's adoption of '90s concepts of register renaming and out-of-order execution are great for a single core. And Intel's HyperThreading with the minor P4 run-time additions passes-the-buck decently in lieu of a complete core redesign (which they haven't done since 1994). But the concept of extending the pipes any further for performance has been largely broken in the P4, and Intel is actually falling back to its last rev of the i686 original, P3. Multiple, _physical_ cores have been the first step. This is little more than slapping in a second set of all the non-SRAM transistors, plus any additional bridging logic, if necessary. AMD HyperTransport requires none -- as HyperTransport can "tunnel" anything, EV6 memory/addressing, I/O tunnels/bridges, inter-CPU, etc... all "gluelessly." Intel MCH GTL+ cannot, and requires bridges between the "chipset MCH" and the "multi-core MCH," adding latency. And there are nagging 32-bit limitations with GTL+ as well (long story). The next logical evolution in microprocessor design is to blur the physical separation between cores. It's the best way without tearing down the entire '70s-induced concept of machine code (operator+ operand, possibly control, at least microcoded internally) and the resulting instruction sets. Instead of discrete, superscalar units of a half-dozen to a dozen, pipelined units, there will be numerous, independent pipes, possibly with their own registers or a number of generic registers, as a single unit. Other than the controlling firmware and/or OS, this is _not_ what software will use. What the software will use are the virtual instantiations that partition this set of pipes and registers, which may very well be dynamic in nature. Let's say I boot Windows, I might instantiate a virtual i686/PAE36 core guaranteeing 100% full Win32 compatibility. Depending on what resources the chip physically has, I will likely even instantiate multiple i686 processors. The concept of multi-CPU and multi-threading has evolved into virtual-cores with virtual-threading. Virtualizing more CPUs with a total number of more pipes/registers than is actual will allow more registers and pipelines to be executing instead of the common 40-50% for superscalar CISC or 60-70% for superscalar RISC. As an "added bonus," this means the 48-bit/256TiB constraint for PAE36 compatibility is _removed_. I.e., you can have a much larger, true memory pool, and any required windowing/ segmentation is done with_out_ paging by the "host" memory model, even though the OS is virtually running in a PAE36 or PAE52 model. This also gives rise to an entirely new platform for virtualization of simultaneous OSes -- be it the same OS, or different OSes. Because cores are virtual, you can have multiple, independent processors with their own registers, memory windows into physical RAM, etc... On the more "consumer" front, this will allow it to work with existing OSes as-is. On the more "load balancing server" front, this will often be paired with software (think EMC/VMWare *SX products) so numerous instances can be dynamically load-balanced across virtual cores -- but far more overhead and increased efficiency is put on the chip. But it is still managed by software (just with reduced context switching overhead in the software). Again, it's really just a consolidation of all the run-time optimizations we have now, along with both multi-core and multi-threading approaches, into a general pool of pipes, registers and organization. Additionally, it breaks the physical constraints of the memory model for the physical hardware, which is a very big issue for our future. To ensure x86/PAE36 and x86-64/PAE52 compatibility in the future, such machines will need to be virtualized or we'll be stuck at 48-bit/256TiB. > As in is it worth anything? Yes -- and almost everything to the future of Microsoft being able to sustain much their existing Win32 codebase which does _not_ port to PAE52 very easily and definitely _not_ with full compatibility. And we have to break the 48-bit/256TiB limitations of PAE52, while still ensuring PAE52 OSes/applications, as well as some legacy PAE36 OSes/applications, still run. The only way is to virtualize the whole freak'n chip so we can instantiate a processor, registers and its memory model -- even if dynamically assigned/ shared. And that's just for end-users, possibly workstations and entry servers. For load-balancing servers, you'll still need a software solution for management. It will be that the hardware just offers far greater efficiency and reduced context switching. In fact, the next consolidation are these virtual core chips in blades, where you not only manage the virtual cores in the individual chips/ blades, but an entire rack of blades as a single unit with multiple OSes spread across. This already exists, but this takes it one step further -- because the processors themselves are virtualized with greatly reduced overhead on the part of the software. > Will it allow a dual simultaneous boot of Linux+WinXP+MaxOS > under Xen or something along those lines? Yes. It will both give more virtualized processors to a single executing OS, as well as create segmented, virtualized processors for independently and simultaneously operating processors. > Even on an SMP machine? First off, remove the Intel-centric notion of "Symmetric" MP (SMP). Secondly, multi-processing and multi-threading are going to merge with traditional register renaming and out-of-order execution. So the traditional concept of "MP" is _dying_. In fact, in the '90s, it really died in general. I know it's hard to think outside the box and traditional thought, but most users don't understand superscalar design in the first place. Those who do understand why AMD has _not_ bothered to adopt Intel SMT (HyperThreading) in Athlon, because it won't benefit (because AMD's cores are 5 years newer in design, and put far more optimizations in the chip to keep pipes full and registers used that to virtualize two sets for the OS to use). > Anyone have any experience/knowledge about this? I can only speculate based on the history of the players involved, as well as what AMD's PAE52 design as well as limitations of the current Athlon core (which is largely the _same_ between both the 32-bit and newer 64-bit versions). But the concept of adding more pipes with lots of stages for timing is only leaving more and more stages in pipes empty, or doing little. There has to be a consolidation of many run-time optimizations inside of the chip, and the best way to do that is to create a bank of pipes, registers, etc... and virtually assemble them into virtual cores that are partitioned with memory as a traditional PAE36 or PAE52 processor (or multi-processor). It's going to solve a _lot_ of issues -- both semiconductor and software. > What level of CPU/hardware(?) does the virt-core support? > And is the virt-core 32bit? You can be certain that the "host" OS (possibly firmware-based?) will be able to instantiate multiple PAE36 and/or PAE52 virtual systems with their own and -- I'll use legacy terminology here (even if it's not technically correct) -- "Ring 0" access. So, technically, there should be possible to run any PAE36 or PAE52 OS simultaneously on the same hardware as any other PAE36 or PAE52 OS. The larger issues of firmware-OS interoperability as well as partitioning resources (memory, disk, etc...) is really more of a political/market issue. I.e., AMD and Intel can provide the platform, but people have to work together to use it. Furthermore, it also means that Intel can continue to best AMD in funding of OEMs and firmware/software vendors, so it still has an advantage in that capacity. I'm sure Apple will be protective of its firmware, and Intel's new, supposed "open" firmware is rather proprietary. As I've repeatedly commented elsewhere, the 2 "most open" hardware vendors right now are AMD and Sun, x86-64 and SPARC, respectively. Intel has not only protected non-programmer aspects of IA-64 heavily, but most of their new platform developments for even IA-32e (EM64T) are _very_proprietary_. IBM is partially doing the same with Power in a microelectronics offering, but it is _not_ the same in its branded Power solutions (among others). So it's not going to solve vendors who require firmware and data organization that is not open and stanardized. We're fine on legacy Win32 platforms, but it's not going to address Mactel, nor solve the problem of existing OSes that don't run under current virtualization solutions because of such proprietary requirements. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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Net installations failing
by Andy Pace 24 Jun '05

24 Jun '05

Why is it that my netinstalls are failing? It's saying that the downloaded image does not match the booted media. i'm using mirror: http://mirror.trouble-free.net/centos/3.4 I've tried installing 4.0 and 3.4 with the same result. Weird huh. This happened to me last week also. Any insight would be greatly appreciated.

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Re: [CentOS] Re: Opteron Mobo Suggestions
by Bryan J. Smith <b.j.smith＠ieee.org> 24 Jun '05

24 Jun '05

From: Kirk Bocek <t004(a)kbocek.com> > Yes, I understand. I also don't have an unlimited budget > If I can get most of the benefit without needing a $300-800 > add-on, that's a big plus. You're talking about an $500-600 mainboard. Then you're talking about $500-800 _per_ dual-core CPU. And then you're gotta factor in the Registered ECC RAM costs. And you're worried about a $125 (3Ware Escalade 8006-2) or $300 (3Ware Escalade 8506-4) controller? Furthermore, the SATA on the nForce MCP is typically only a single, 133MBps PCIe x1 channel. You'll get 533MBps out of the 8506-4 in a PCI slot at 64-bit @ 66MHz. > I conceptually understand iSCSI, but how would I use a GbE > NIC in a backup solution? What do you think iSCSI is? It's storage over IP, but just with an additional a host processor in the GbE to off-load overhead. If you don't have the money for a HBA GbE, then just do straight GbE. Build an out-of-band IP network segmented off on a 2nd GbE connection in each system. [ HINT: I'm exploring the issues of real-time backup and discuss near-line storage, virtual tape libraries and, in a future article after that, out-of-band networks and "cheap" SANs. All from the standpoint of a sysadmin, and not so much network/storage engineering. ] > Don't forget that a backup solution would depend on > hot-pluggability. That's why I was thinking of USB/IEEE- > 1394. Mistake on a server. You don't want to hot-plug consumer interconnects. One issue, bam! Kernel panic. Use an out-of-band IP network over a 2nd GbE connection to what you need elsewhere on the network. I have been recommending this where cost is a factor. > Cool, I will take a look at HP's offerings. Do you have any > motherboards alone that you would recommend? It's difficult because of the limited designs. A lot of mainboards "cut corners" for cost considerations. Even the Tyan 4885 puts _all_ I/O on _one_ CPU. The HP DL585 follows the AMD reference. -- Bryan J. Smith mailto:b.j.smith@ieee.org

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