"Bryan J. Smith" b.j.smith@ieee.org wrote:
Digital EV6 platforms have ports (up to 16) into a "crossbar switch." The logical front-side bus is also 64-bit, including S462. Again, any claims of "dual DDR" is actually an interleaving hack, done in an attempt to reduce latency and increase overall throughput. But it is not the same as S939/940's _true_ 368 traces for a _true_ 128-bit DDR.
I should point out that it _is_ possible to have two (2) or even more DDR channels connected to an EV6 crossbar. And you could have _multiple_ CPU, which are on different "ports," bursting traffic to different memory channels on different memory "ports."
But _none_ of the "dual DDR" Athlon implementations did that AFAIK. Only Digital Alpha 264 systems used multiple 64-bit memory ports. It was commonly 2, 4 or 8 EV6 Alpha 264 CPUs, with 2 or 4 SDR/DDR memory channels and a few 64-bit PCI bridges, to round out the maximum of 16 "ports" into the crossbar.
The Athlon MP (AMD762 northbridge) platform used only 5 ports -- 2 CPU (each CPU had its own interconnect), 1 memory, 1 PCI32@266MHz (AGP2.0 aka x4) and 1 PCI64@33 (AMD766) or 1 PCI64@66 (AMD768). Supposedly up to four (4) AMD762 northbridges could be used in a system -- connected to each other using the PCI32@266MHz channel (normally used by AGP). But no PC mainboard I saw ever did (and by the time API came around, they were only using one AMD762 for Alpha 264 systems).