On Wed, 2005-06-29 at 12:20 +0800, Feizhou wrote:
I thought they have done away with the high memory bounce buffers?
Correct. On x86-64, they have.
Can you explain what Andi means by this? ----quote---- Current X86-64 implementations only support 40 bit of address space, but we support upto 46bits. This expands into MBZ space in the page tables. -Andi Kleen, Jul 2004 ----quote---- Does it mean that we don't need no fancy tweaks to get direct addressing for over 1G or over 4G?
Correct. I haven't looked at how Linux/x86-64's paging works, but as long as they at least support 40-bit, they're good for the current generation of AMD64.
Some EM64T processors only do 36-bit, the new ones do 40-bit (with a new TLB-page table).
Is that hack for Athlons limited/useful only to Athlon MP boards with the Linux option in BIOS or do Opterons also need that?
It hack is _solely_ for Athlon MP, and it's quite limited in scope. In a nutshell, it really enables features of the Athlon MP that _breaks_everything_. Hence why it's rare, and Linux is the only OS with the hack.
Opteron with its x86-64 PAE (52-bit) mode is completely linear, up to 40-bit in its current, legacy EV6 logic implementation. The 52-bit virtual addressing using PAE allows 32-bit, legacy 36-bit PAE as well as new 52-bit PAE applications to run.