Sorry (I'm start proof-reading before I hit "send" ;-).
On Tue, 2005-06-28 at 22:50 -0500, Bryan J. Smith wrote:
48-bit virtual addressing is i386 onward: 16-bit segment + 32-bit register
16-bit segment (register) + 32-bit offset (register)
The i386 onward normalizes ... There is no A36 "hack" like there was for 8086/8088 though.
I meant there is no A32 "hack" for 32-bit.
But there is the A32-35 "PAE hack," which works a bit different, as I explained.
PAE in x86-64 ... the 16-bit segment and 32-bit offset are connected "Long" MSB of offset against the LSB of the register.
Ugh, that last part should read ... "Long" MSB of the offset (register) against the LSB of the segment (register).
Athlon 64/Opteron is designed as a _minimal_ core redesign from Athlon. This includes both the addressing registers and the limitations of EV6. Everything else has been the addition of 64-bit paging table entries, the move of the memory and I/O interconnects internally (still EV6- based), etc...