On Friday 24 June 2005 21:14, Bryan J. Smith wrote:
On Fri, 2005-06-24 at 20:16 -0400, Peter Arremann wrote:
Ok - so the PAE36 mechanism is the same, the 36bit addresses are the same just the address ranges that are reserved for special use are different?
Ugh, sigh, you're thinking like a programmer. ;-> You have to separate the logical (programmer) from the physical (engineer) concepts.
Sorry I guess. Don't know how that happened - went to a electrical engineering school, specialized in micro electronics :-)
That would require an additional level of page translation though or a really substential redesign - so its in my opinion unlikely that they do...
Again, thinking like a programmer. ;->
*whistles innocently*
The Athlon was _already_ designed for 40-bit EV6 _physically_ and eventual "Long Mode" programmatically. The TLB in the Athlon is _not_ designed for GTL, but EV6. It only works like a GTL when so commanded. ;->
Ok, now I have to ask even more questions :-) If the physical bus is EV6, the internals are EV6 and the programming model doesn't matter as you said before - then why would the TLB on the athlon emulate a GTL?
Intel GTL is only capable of 32-bit.
GTL (P5) yes - but that doesn't have PAE36 either... But we're talking PAE here - so GTL+ aera...
I meant GTL and all derivatives ... GTL+, AGTL+, etc...
Then you're clearly wrong calling it a 32bit addressed bus...
The address pins are even labeled up to A35 Download any of the PPro and newer spec sheets (except mobile cpus that don't support PAE). The Pentium II 300Mhz Specs is a good example. Quote from page 75: "The Address signals define a 2^36-byte physical memory address space." document id 24365702.pdf
Of course! Because if it didn't, it wouldn't be able to page in beyond 4GiB. @-ppp Yes, but the TLB compatibility and other issues are involved, things that GTL and all derivatives _never_ addressed.
In a nutshell, Intel PAE36 processors on even AGTL+ are _incapable_ of the combination of both _physical_ and _logical_ addressing to do anything but paging above 4GiB. That's my point.
Define paging then - I can access >4GB on an EMT64 - It just lacks and IO mmu to do coordinate dma from a 32bit device to a memory region > 4GB... but if I just do a memory access, then there is no issue - no paging nessecary...
AMD solved the problem by using EV6, which is _nothing_ like GTL-based busses. It goes far deeper than you realize.
they solved the 32bit IO issue with by morphing their agpgart into a minimalistic io mmu ...
Peter.