On Thu, 8 Sep 2005 at 11:33am, Bryan J. Smith wrote
Peter Arremann loony@loonybin.org wrote:
less memory bandwidth for each cpu and so on.
Okay, this is _misleading_. You're thinking Intel SMP.
Opterons _always_ have 128-bit of DDR (2 channels) per CPU. Opteron uses NUMA (and HyperTransport partial meshes for CPU-I/O). There is _no_ "less memory bandwidth for each cpu". That is a trait of Intel SMP [A]GTL+, not AMD NUMA/HyperTransport.
Yes, if the Opteron has to access memory over on another CPU, then that is a performance issue. If the other CPU is on another mainboard, then yes, contention can happen there.
One has to be even more careful with terminology these days. You can see less memory bandwidth per *core* with dual core Opterons. But, as you point out, each CPU (socket -- what should we call it?) has, essentially, its own bank of memory.