[Arm-dev] [PATCH v0 01/20] arm64: gicv3: its: Ignore Chacheability fields in GITS_BASER

From: Tirumalesh Chalamarla <tchalamarla at caviumnetworks.com>

Implement erratum:

 24313 - Pointer Memory Attribute Fields with Wrong Access Type

These fields have a wrong access type of RO/RAZ. Ignoring the bits.

Signed-off-by: Tirumalesh Chalamarla <tchalamarla at cavium.com>
Signed-off-by: Robert Richter <rrichter at cavium.com>
Signed-off-by: Vadim Lomovtsev <Vadim.Lomovtsev at caviumnetworks.com>
---
 arch/arm64/Kconfig               | 7 +++++++
 drivers/irqchip/irq-gic-v3-its.c | 4 ++++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 318175f..68ef1f1 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -243,6 +243,13 @@ config ARCH_THUNDER
 	help
 	  This enables support for Cavium's Thunder Family of SoCs.
 
+config THUNDERX_PASS1_ERRATA_24313
+	bool "Cavium ThunderX erratum 24313"
+	depends on ARCH_THUNDER
+	def_bool ARCH_THUNDER
+	help
+	  Enable workaround for erratum 24313.
+
 config ARCH_VEXPRESS
 	bool "ARMv8 software model (Versatile Express)"
 	select ARCH_REQUIRE_GPIOLIB
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 1b7e155..a46040f 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -802,7 +802,11 @@ static int its_alloc_tables(struct its_node *its)
 	int i;
 	int psz = SZ_64K;
 	u64 shr = GITS_BASER_InnerShareable;
+#ifdef CONFIG_THUNDERX_PASS1_ERRATA_24313
+	u64 cache = 0;
+#else
 	u64 cache = GITS_BASER_WaWb;
+#endif
 
 	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
 		u64 val = readq_relaxed(its->base + GITS_BASER + i * 8);
-- 
2.4.3