[CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing

[Bryan J. Smith]

On Fri, 2005-06-24 at 23:22 -0400, Peter Arremann wrote:
> Hmmm... GTL is a parallel bus... Therefore the width of the bus is defined by 
> either address or data width. GTL and all variants are 64bit data, so that 
> can't be the reason for calling it a 32bit bus. 

Sigh, I _explicitly_ used the adjective "address."  If I slipped once or
twice, I apologize.  This is pretty a good sign to end the thread,
because it's just argumentative at this point.  ;->

BTW, GTL can be _wider_ than 64-bit.  It can be multiples of 64-bit, but
it is still a "shared" bus/hub configuration.  Many 2 and 4-way Xeon
servers use 128-bit or even 256-bit shared buses to the MCH, and then
the memory.

EV6 is an up to 16 multi-point cross-bar switch configuration of
independent, 64-bit wide buses.  E.g., the dual Athlon MP uses 2
_independent_ buses from is crossbar switch "northbridge."

> Since the accesses have to be aligned on 8 byte boundries the lower the bus 
> does not carry A0, A1, A2. 

Of course.  Paragraphs are 256 bytes.  Paging is typically 4KiB (unless
4MiB is enabled, which not-well-regression-tested results on Athlon, but
it doesn't do anything for the Athlon anyway).

> On the Pentium (GTL bus) there are the address pins A3 through A31. [Pentium 
> MMX embedded version, couldn't find the regular P5/P54C docs anymore. 
> www.intel.com/design/intarch/applnots/27320602.pdf]
> Then, GTL+, support for PAE36, has address bits for 36bit adressing - A3 
> through A35. [Pentium II processor specs: 
> ftp://download.intel.com/design/intarch/datashts/27326801.pdf] 
> Finally you've got the high end stuff like a Xeon MP, 64bit... Address lines 
> A3 through A39 - so space for 40 bit physical addresses. 
> [http://download.intel.com/design/Xeon/datashts/30675401.pdf&e=7152]
> So, if the different number of address lines doesn't change the width of a 
> bus, what does? :-)

Socket-A/462 via EV6 doesn't have "fixed" address lines if you bothered
to check (it only has 13 x 2).  The existence of an actual, physical
trace is not how addressing works.

But at this point, let's just forget this whole thread because it's
obvious that you're not interested in hearing me out, just hearing
yourself out.


-- 
Bryan J. Smith                                     b.j.smith at ieee.org 
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