[CentOS] Re: Offtopic Posts [was Re: [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing]

[Bryan J. Smith]

On Tue, 2005-06-28 at 22:27 -0400, Peter Arremann wrote:
> It wouldn't bother me as much if he didn't go with this all over the place. 

Because it's _very_complex_ to understand.

Even you wanted to break it down to board layout.  Of course there is
36-bit addressing, because you can't access up to 64GiB without it.  ;->

It's similar to someone screaming "why doesn't this 256MB DIMM work!"
when your mainboard supposedly supports 256MB DIMMs, even a higher SDRAM
technology than the DIMM.  It has nothing to do with the traces and
support, but how it's actually implemented in the memory controller (or
in our case, the TLB-page table).

Now that's an over-simplification, but as I've explained before, 

> Search google for PAE52 and filter out the non technical docs (or try PAE52 
> +athlon). Only Bryan's posts. 

Dude, hit _both_ AMD _and_ Intel "programmer" guides.  They discuss how
PAE52 is a 7-part addressing model for 48-bit addressing that is also
compatible with PAE36 model.

It's not only how a PAE52 OS can run PAE36 (and 32-bit) binaries, but
also why PAE52 program's can't use PAE36 libraries or vice-versa without
software-level translation.

PAE52 is the model _well_known_ among people building x86-64 software.

> Search for Athlon64 and EV6 - and the only one that says it is the same bus 
> and not hyperthreading (with a few legacy remainders of EV6 like the location 
> of certain memory locations) - again only Bryan. 
> People that say AthlonMP can go >4GB linear? Only Bryan.

I'm frantically trying to find the post from the LKML.

Note, AFAIK, the Athlon MP was _never_ implemented in a board that
supported over 4GiB.  But _all_ so-called "32-bit" Athlons _do_ support
PAE36, including the flag being set in the processor as well so _all_
PAE36 OSes can see it.  It goes back to its EV6 roots.

> Posts that don't acknoledge that Athlon64 and 32bit athlon are indeed based on 
> the same core but have major differences (i.e. 64bit extensions, ht bus 
> rather than ev6, ...) ? you guessed it - only Bryan. 

Athlon 64/Opteron _uses_ EV6!  EV6 is tunneled over HyperTransport!
It's how other bus logic, including GTL on Intel platforms, is tunneled.

People think Athlon 64/Opteron implements HyperTransport like a
traditional MCH.  Indeed, both the Apple G5 as well as HyperTransport
between the "northbridge" and "southbridge" for Intel GTL+ processors on
nVidia and SiS do this.

But in the Athlon 64/Opteron, the traditional "northbridge" is moved
into the CPU.  The CPU handles the EV6 logic internally, and has direct
connections to both the DDR SDRAM channels as well as its own
HyperTransport interconnect to other CPUs.

By your "simplification," the "narrow bus" design of HyperTransport
would mean its _incapable_ of supporting 64-bit GTL or EV6 logic.  Dude,
you just have to dig into the design of the core to understand this.
The info is out there man!

Anyhoo, the 40-bit physical addressing limitation of Ev6 comes into play
in x86-64 as it is currently implemented in both AMD64 _and_ EM64T.
Intel has extended GTL to support the same limitations as EV6.

I'm sure the 4th generation of both Intel x86 and AMD x86 will overcome
this.

> Sorry, but for me, that's a little weird... So many engineers in this world 
> and only one person can see the truth?

Dude, get off the "truth" non-sense.

PAE52 is a reality.
The foundations and limitations of GTL and EV6 are reality.

Most people don't understand how very different the Athlon is because
Athlon only emulates most aspects of x86/GTL, even though it does not
use it natively.
And Athlon 64/Opteron is an evolution of EV6 into its current, multi-
point, EV6-addressed NUMA/HyperTransport interconnect.


-- 
Bryan J. Smith                                     b.j.smith at ieee.org 
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