[CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing

Fri Jun 24 06:09:21 UTC 2005
Bryan J. Smith <b.j.smith at ieee.org>

On Fri, 2005-06-24 at 01:37 -0400, Peter Arremann wrote:
> How does that work? :-) 

It works on the reality that the 32-bit Athlon and 64-bit Athlon use the
_same_ 40-bit/1TiB EV6 addressing to memory (as well as tunneled over
HyperTransport to other CPUs and I/O in the case of the latter).  In
reality, they are the same core designs too (the latter just being
revamped ALU with 64-bit features, more 128-bit XMM registers and the
evolution of its on-CPU AGPgart to the I/O MMU).

Normally the 32-bit Athlon is limited in its addressing to 32-bit/PAE36
(4/64GiB) for Intel GTL compatibility at the BIOS, OS, etc...  If you
have a BIOS that lets the 32-bit Athlon break 32-bit/PAE36 Intel GTL
compatibility, and pair it with an OS that does the same, then you can
have the _full_ support of 32-bit Athlon's EV6 addressing architecture.
In fact, EV6 is _nothing_ like GTL, but it just emulates it.  That
includes it looking like a "SMP bus" in the case of Athlon MP, when --
in fact -- it's an "MP switch."

If you want to know more about the non-PAE36 >4GB Linux hack and the few
Athlon MP mainboards with BIOSes that support it, read up on the LKML
circa February 2004.


-- 
Bryan J. Smith                                     b.j.smith at ieee.org 
--------------------------------------------------------------------- 
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