[CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing

Fri Jun 24 12:42:48 UTC 2005
Bryan J. Smith <b.j.smith at ieee.org>

On Fri, 2005-06-24 at 02:51 -0400, Peter Arremann wrote:
> Hmmm - The GTL bus uses 36bit for address... So if you get a license from 
> Intel and build your own device, it can address 36bits directly without any 
> games. PAE36 is a mmu concept that allows a 32 bit OS to have 16 4GB pages 
> (hence the name Page Address Extensions 36 bits...) 

Yes, the key word there is that it "pages."  BTW, it's not 16 x 4GB
pages, but 120 x 512MB pages into the lower 8 x 512MB memory.

Intel GTL is _still_ a 4GB platform with paging above 4GB up to 64GB.
It is literally like using old EMS in DOS.

> So if you have a 32 bit athlon, you get 4GB ram... To go above that, you need 
> more bits.

Sigh ... the 32-bit Athlon uses _40-bit_ EV6.  I only used the term "32-
bit Athlon" to market differentiate from the "64-bit Athlon/Opteron."
In reality, _both_ products use the same core with 40-bit EV6
addressing.  The latter just also offers a 48-bit/PAE52
programming/register "Long Mode", whereas the former only offers a 32-
bit/PAE36 programming/register mode.

> Those bits need to be stored in a separate register since all your 
> apps and os only have 32bit

36-bit -> 16-bit segment + 32-bit offset = 36-bit (4-bits overhang).

On Intel GTL, it pages above 4GB, as you mentioned.

On AMD EV6, it also does it linearly in hardware for GTL compatibility.
_Unless_ you have an Athlon MP mainboard with the BIOS and a Linux
kernel that offers _true_ access.  It that _avoids_ paging in hardware
above 4GB, significantly improving performance.

The Athlon64/Opteron just now have a formal mode called "Long Mode"
where the 16-bit segment is the "top bits 33-48" with the 32-bit offset
= 48-bit/256TiB.  _Physically_ Athlon64/Opteron are still limited to
EV6's 40-bit/1TiB addressing of the platform, same as 32-bit Athlon.

People often get confused on _physical_ platform (board engineering-
level) addressing versus _logical_ "programmer" addressing.

>  - and then you need to have a mmu that can combine those two into the
> physical address... And the combining of an offset and a segment is
> what PAE36 is all about... See where my confusion comes in? :-) 

Yes, reference above.

> Sorry to make you even more work but I searched the LKML archives and
> couldn't find anything :-( Could you please send me a direct link?

I'll find it.  It was from a gentlemen from AMD that discussed it in a
thread right after Intel announced EM64T.  Linus & co. were talking
about how EM64T is still using a 32-bit platform underneath.  The AMD
gentlemen commented how they a few vendors had a BIOS option "Linux" for
the memory access, and the Linux kernel could support linear addressing
above 4GB.


-- 
Bryan J. Smith                                     b.j.smith at ieee.org 
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