[CentOS] [OT] Memory Models and Multi/Virtual-Cores -- WAS: 4.0 -> 4.1 update failing

Sat Jun 25 00:16:50 UTC 2005
Peter Arremann <loony at loonybin.org>

On Friday 24 June 2005 18:44, Bryan J. Smith <b.j.smith at ieee.org> wrote:
> From: Peter Arremann <loony at loonybin.org>
>
> > And that's exactly the part I don't get - if you have a 32bit address
> > model then you have to use PAE of some sort (compatible to Intel PAE36 or
> > not) to get to address more than that memory...
>
> The BIOS hack basically says "don't be stupid" >4GB.  It tells the Athlon
> MP to the PAE36 addresses linearlly, instead of paging in GTL compatible
> fashion.
Ok - so the PAE36 mechanism is the same, the 36bit addresses are the same just 
the address ranges that are reserved for special use are different? 


> With that said, do you mean _beyond_ 36-bit/64GiB?
Sorry meant beyond 32bit address space / 4GB. 

> In reality, if the hack uses Linux/x86-64, it could very well be that it
> puts the Athlon MP in "48-bit/256TiB Long Mode" and translates addreses
> linearlly. The Athlon MP wouldn't offer PAE52, no.  But it _could_ offer
> PAE36 windows in a 48-bit (40-bit physical EV6) space.
That would require an additional level of page translation though or a really 
substential redesign - so its in my opinion unlikely that they do...

> Intel GTL is only capable of 32-bit.
GTL (P5) yes - but that doesn't have PAE36 either... But we're talking PAE 
here - so GTL+ aera... The address pins are even labeled up to A35
Download any of the PPro and newer spec sheets (except mobile cpus that don't 
support PAE). The Pentium II 300Mhz Specs is a good example. Quote from page 
75: "The Address signals define a 2^36-byte physical memory address space." 
document id 24365702.pdf

Peter.