[CentOS] [OT] Memory Models and Multi/Virtual-Cores -- =?iso-8859-1?q?WAS=3A=094=2E0-?=> 4.1 update failing

Wed Jun 29 05:01:52 UTC 2005
Bryan J. Smith <b.j.smith at ieee.org>

On Wed, 2005-06-29 at 00:26 -0400, Peter Arremann wrote:
> Unfortunately AMD gets punished for Intel's lazyness. Intel does not want to 
> implement an iommu.

Actually, it was more like the fact that because AMD doesn't have all
processors connect to a "hub" over the same connection, AMD was _forced_
to develop GARTs for _all_ I/O in the so-called "32-bit" Athlon MP.
The I/O MMU in the Athlon 64 and Opteron is just an evolution of that.

GARTs and I/O MMU's are _nothing_ new in RISC platforms that are
switched or meshed.  Intel just hasn't developed such a beast, and 3rd
party proprietary Xeon or Itanium systems that do use "glue" (and costly
system redesign) when they need to.  AMD was just the first to offer a
commodity one that comes built-in (along with other goodies).

The "bonus" is that an I/O MMU solves the _real_world_ issue that some
I/O cards and drivers only do 32-bit addressing, and are incapable of
handling memory mapped I/O above 4GiB.

> RedHat and others don't want to have to support two separate kernels - so
> they limit IO to the lowest 4GB no matter if you're running an Opteron
> or EM64T. 

?  I was unaware this is how they handled Opteron.  I thought Red Hat
_dynamically_ handled EM64T separately in their x86-64 kernels, and that
was a major performance hit.

I need to go research this ...

> I assume this quote is from http://lwn.net/Articles/117783/? about the 4th 
> page table level? 
> The memory that your process can use is split in several different segments as 
> listed in that article. The processes need to have (among other stuff) access 
> to the kernel, shared memory and so on. For that they have to select a 
> mapping - and the mapping was simply selected to support 46 bits... 

Actually, it sounds like they were good with 3-level at 39-bit for the
current generation of x86-64, which only does 40-bit/1TiB.  Unless, of
course, that was a compatibility issue with running 32-bit, PAE36 and
PAE52 program simultaneously.

I wonder if the 4-level is a performance hit, which is not ideal.  Maybe
there is a way to disable it if there is no compatibility issue?


-- 
Bryan J. Smith                                     b.j.smith at ieee.org 
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