Hi :) On Tue, Mar 22, 2011 at 3:59 PM, Vladimir Budnev <vladimir.budnev at gmail.com> wrote: [...] > But... as i sad we have following slots > CPU1 cpu1-a1 cpu1-a2 cpu1-a3 cpu1-b1 cpu1-b2 cpu1-b3 > CPU2 cpu2-a1 cpu2-a2 cpu2-a3 cpu2-b1 cpu2-b2 cpu2-b3 > > We have modules placed in such way: > +------------+------------+------------+------------+------------+------------+------------+ > | | V | V | V | V | > free | free | > +------------+------------+------------+------------+------------+------------+------------+ > | CPU1 | cpu1-a1| cpu1-a2 | cpu1-a3 | cpu1-b1 | cpu1-b2| cpu1-b3 | > +------------+------------+------------+------------+------------+------------+------------+ > > > +------------+------------+------------+------------+------------+------------+------------+ > | | V | V | V | V | > free | free | > +------------+------------+------------+------------+------------+------------+------------+ > | CPU2 | cpu2-a1| cpu2-a2 | cpu2-a3 | cpu2-b1 | cpu1-b2| cpu1-b3 | > +------------+------------+------------+------------+------------+------------+------------+ > > Definetely there is something with memory banks,becasue replacinbg moudels > changed the mce messages, but what exactly...or iv interpreted all wrong? This isn't an optimal setup (performance-wise). You should always populate complete slots in multiples of 3 to get the full bandwidth. In your case, you've got cpu1-b[2|3] and cpu2-b[2|3] with no DIMMs so that would affect your performance. HTH Rafa