From: Peter Arremann loony@loonybin.org

US-V has been canceled...

By Sun, yes. They believe they will transition to Opteron sooner than they thought. All I said was that it had been "planned through" US-V, including the design work done. My bet is that the engineers had finished the core design, even if not fully optimized, and that's when they were canned. It's still an option in the back of Sun's pocket.

[ I.e., the core design occurs _years_ before products become available. E.g., even the latest Opterons are based on the 1997 core design. And until the Pentium 4 came out (just a refit), the Pentium 3 was still based on the 1994 Pentium Pro core. ]

Fujitsu has yet to weigh in and possibly pick up the design. They have been designing SPARC modules (better ones IMHO) for a long time. All it takes is 1 customer who needs SPARC binary compatibility.

There was an equal battle over the Alpha 364, with OpenVMS the driver. Especially since OpenVMS/Itanium was _slower_ (than an Alpha 264 from 3 years earlier no less!). But once [quality] emulators became available, that killed it.

I don't think you'll see the same with SPARC, but I could be wrong. If the need by just 1 major user is there, you can be sure Fujitsu will come out with a PRIMEPower upgrade that uses the design.

I never said Sun would release an UltraSPARC V, I just said it has been planned (i.e., designed). Sun has made it known that as of right now, UltraSPARC IV is the "end-of-the-line" for Solaris, and given how Solaris is working on Opteron, I don't blame them.

But HP is _still_ selling Alpha 264s because of OpenVMS. ;-> A platform they have tried to kill off again and again and again.

US-IIIi is up to 4 way...

I _never_ said it wasn't. I just said the 1-2 ways are comparable to a typical PC design**.

But after 2-way, it's much better to go with a US-III or US-IV, kinda like it's much better to go with an Opteron instead of a Xeon beyond 2-way**. ;->

-- Bryan

**NOTE: This is a recurring theme. You seem fixated on the assumption that a system that uses a single-point-of-contention design (namely the Intel MCH aka "northbridge") approach would _always_ be faster. You seem to lack the understanding beyond the real design contraints of a partial mesh interconnect on a real system interconnect (and not just a peripheral interconnect hacked on as a system interconnect). You have degraded most of my commentary as a "that's a chipset issue." You seem to have a very limited understanding outside of the traditional PC CPU-to-memory or CPU-to-I/O via a "chipset" and that's why you keeping missing my points on Opteron, UltraSPARC, etc...

Not to mention this thread was just about finding a solution with hot-swappable components. I left it at that _until_ you wanted to assert all sorts of things (using "builds" as a benchmark for servers, even computational ones).

-- Bryan J. Smith mailto:b.j.smith@ieee.org