Hello CentOS Community,
So I bought a NIC (using the Intel 82579V chipset) that supports Dual RX and TX queues , my goal with that is so iam able to see and use two IRQs in /proc/interrupts and hence be able to take advantage of 2 cores on my CPU. Instead I only see one IRQ being used, and hence only one CPU core.. Please see below.
Advisement is appreciated!
Alex
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LAN support Gigabit (10/100/1000 Mbits/sec) LAN subsystem using the Intel® 82579V Gigabit Ethernet Controller http://www.intel.com/content/www/us/en/motherboards/desktop-motherboards/des...
[root@nodeA LabTests]# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 {...}
33: 180364 0 0 0 IR-PCI-MSI-edge eth0
DMESG:
e1000e 0000:00:19.0: eth0: (PCI Express:2.5GT/s:Width x1) 00:22:4d:9d:55:13 e1000e 0000:00:19.0: eth0: Intel(R) PRO/1000 Network Connection e1000e 0000:00:19.0: eth0: MAC: 10, PHY: 11, PBA No: FFFFFF-0FF
e1000e 0000:00:19.0: irq 33 for MSI/MSI-X e1000e 0000:00:19.0: irq 33 for MSI/MSI-X ADDRCONF(NETDEV_UP): eth0: link is not ready e1000e: eth0 NIC Link is Up 100 Mbps Full Duplex, Flow Control: Rx/Tx e1000e 0000:00:19.0: eth0: 10/100 speed: disabling TSO ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready eth0: no IPv6 routers present usb 1-1.5: USB disconnect, device number 3 lo: Disabled Privacy Extensions e1000e 0000:00:19.0: irq 33 for MSI/MSI-X e1000e 0000:00:19.0: irq 33 for MSI/MSI-X ADDRCONF(NETDEV_UP): eth0: link is not ready e1000e: eth0 NIC Link is Up 100 Mbps Full Duplex, Flow Control: Rx/Tx e1000e 0000:00:19.0: eth0: 10/100 speed: disabling TSO ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready eth0: no IPv6 routers present Intel® 82579V
On 6/8/2013 9:46 PM, Alex Flex wrote:
So I bought a NIC (using the Intel 82579V chipset) that supports Dual RX and TX queues , my goal with that is so iam able to see and use two IRQs in /proc/interrupts and hence be able to take advantage of 2 cores on my CPU. Instead I only see one IRQ being used, and hence only one CPU core.. Please see below.
Advisement is appreciated!
wait, the 82579 is just a PHY layer for the Intel 6 Series Express CPU chipset's built in MAC (p67, z68, hm67, etc chipsets for the Sandy Bridge family of desktop/mobile CPUs). That combination is also a 'entry level' desktop/workstation or 'mobile embedded' grade ethernet interface, not really a server grade interface at all.
regardless, its a single device. single devices, regardless of how many queues they may happen to have, are not reentrant, and can not deal with multiple concurrent IRQ handlers poking at their registers at the same time.
you might have more luck with something like this http://ark.intel.com/products/59062/Intel-Ethernet-Server-Adapter-I350-T2 but even so, I doubt it will use multiple CPU cores at the same time, but it probably WILL significantly reduce the CPU overhead of dealing with high volume ethernet traffic.
Hello John,
Thanks for the informative reply, do you know what Intel would mean by advertising the NIC with "Performance — Two Queues (Tx & Rx) " then?
If i understand you correctly, are you confirming to me that only a Dual port NIC will deliver different IRQs?
Alex
On 06/08/2013 11:44 PM, John R Pierce wrote:
wait, the 82579 is just a PHY layer for the Intel 6 Series Express CPU chipset's built in MAC (p67, z68, hm67, etc chipsets for the Sandy Bridge family of desktop/mobile CPUs). That combination is also a 'entry level' desktop/workstation or 'mobile embedded' grade ethernet interface, not really a server grade interface at all. regardless, its a single device. single devices, regardless of how many queues they may happen to have, are not reentrant, and can not deal with multiple concurrent IRQ handlers poking at their registers at the same time. you might have more luck with something like this http://ark.intel.com/products/59062/Intel-Ethernet-Server-Adapter-I350-T2 but even so, I doubt it will use multiple CPU cores at the same time, but it probably WILL significantly reduce the CPU overhead of dealing with high volume ethernet traffic.
Am 09.06.2013 06:46, schrieb Alex Flex:
Hello CentOS Community,
So I bought a NIC (using the Intel 82579V chipset) that supports Dual RX and TX queues , my goal with that is so iam able to see and use two IRQs in /proc/interrupts and hence be able to take advantage of 2 cores on my CPU. Instead I only see one IRQ being used, and hence only one CPU core.. Please see below.
First, yes, the NIC will only use one IRQ. That is as it should be.
Second, no, that doesn't mean that only one CPU core will be used.
Very little work is done inside the ISR, because that work must be strictly serialized. The bulk of the work is done outside interrupt context, and that work is distributed over the CPU cores by the scheduler. Distributing the IRQs would unnecessarily complicate things without buying you any performance improvement.
HTH T.
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Alex Flex -
John R Pierce -
Tilman Schmidt