Merged. This will be available in the next update.
On 12/12/2016 02:29 AM, Vadim Lomovtsev wrote:
Hi Jim,
Could you please consider this patch to be applied to 7.3 kernel build?
WBR, Vadim
On Mon, Dec 12, 2016 at 12:18:59AM -0800, Vadim Lomovtsev wrote:
From: David Daney david.daney@cavium.com
Some (defective) PCIe devices are not able to reliably do link retraining.
Check to see if ASPM is possible between link partners before configuring common clocking, and doing the resulting link retraining. If ASPM is not possible, there is no reason to risk losing access to a device due to an unnecessary link retraining.
Signed-off-by: David Daney david.daney@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com
drivers/pci/pcie/aspm.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 2dfe7fd..abad79e 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -351,12 +351,26 @@ static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist) return; }
- /* Get upstream/downstream components' register state */
- pcie_get_aspm_reg(parent, &upreg);
- child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
- pcie_get_aspm_reg(child, &dwreg);
- /*
* If ASPM not supported, don't mess with the clocks and link,* bail out now.*/- if (!(upreg.support & dwreg.support))
return;- /* Configure common clock before checking latencies */ pcie_aspm_configure_common_clock(link);
- /* Get upstream/downstream components' register state */
- /*
* Re-read upstream/downstream components' register state* after clock configuration*/
child = list_entry(linkbus->devices.next, struct pci_dev, bus_list); pcie_get_aspm_reg(child, &dwreg);
/*
-- 2.5.5