To enable evaluation of QDF2400v1 hardware, apply two CPU errata workarounds. These errata will be fixed in future hardware, so these patches shouldn't be necessary for more than one release, and if carrying them for that limited period time becomes a burden they can be dropped.
Signed-off-by: Christopher Covington cov@codeaurora.org --- ...64-Define-Qualcomm-Technologies-ARMv8-CPU.patch | 44 ++++ SOURCES/4001-arm64-Workaround-Falkor-E1003.patch | 149 ++++++++++++ SOURCES/4002-arm64-Workaround-Falkor-E1009.patch | 257 +++++++++++++++++++++ SOURCES/config-centos-sig | 3 + SPECS/kernel-aarch64.spec | 15 +- 5 files changed, 467 insertions(+), 1 deletion(-) create mode 100644 SOURCES/4000-arm64-Define-Qualcomm-Technologies-ARMv8-CPU.patch create mode 100644 SOURCES/4001-arm64-Workaround-Falkor-E1003.patch create mode 100644 SOURCES/4002-arm64-Workaround-Falkor-E1009.patch
diff --git a/SOURCES/4000-arm64-Define-Qualcomm-Technologies-ARMv8-CPU.patch b/SOURCES/4000-arm64-Define-Qualcomm-Technologies-ARMv8-CPU.patch new file mode 100644 index 0000000..0e353bc --- /dev/null +++ b/SOURCES/4000-arm64-Define-Qualcomm-Technologies-ARMv8-CPU.patch @@ -0,0 +1,44 @@ +From d19773b345cd01e6735602c8b85650c792b62941 Mon Sep 17 00:00:00 2001 +From: Shanker Donthineni shankerd@codeaurora.org +Date: Tue, 18 Oct 2016 20:43:19 -0500 +Subject: [PATCH] arm64: Define Qualcomm Technologies ARMv8 CPU + +This patch adds the cputype info for Qualcomm Technologies ARMv8 +CPU implementer ID 0x51 and part number for Falkor in cputype.h. + +Signed-off-by: Shanker Donthineni shankerd@codeaurora.org + +[Rebase from vanilla 4.5 onto CentOS 7.3 AltArch] +Signed-off-by: Christopher Covington cov@codeaurora.org +--- + arch/arm64/include/asm/cputype.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h +index f94a4c8..423f244 100644 +--- a/arch/arm64/include/asm/cputype.h ++++ b/arch/arm64/include/asm/cputype.h +@@ -77,6 +77,7 @@ + #define ARM_CPU_IMP_APM 0x50 + #define ARM_CPU_IMP_CAVIUM 0x43 + #define ARM_CPU_IMP_BRCM 0x42 ++#define ARM_CPU_IMP_QCOM 0x51 + + #define ARM_CPU_PART_AEM_V8 0xD0F + #define ARM_CPU_PART_FOUNDATION 0xD00 +@@ -90,9 +91,12 @@ + + #define BRCM_CPU_PART_VULCAN 0x516 + ++#define QCOM_CPU_PART_FALKOR 0x800 ++ + #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) + #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) + #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) ++#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) + + #ifndef __ASSEMBLY__ + +-- +1.8.3.1 + diff --git a/SOURCES/4001-arm64-Workaround-Falkor-E1003.patch b/SOURCES/4001-arm64-Workaround-Falkor-E1003.patch new file mode 100644 index 0000000..d7e5855 --- /dev/null +++ b/SOURCES/4001-arm64-Workaround-Falkor-E1003.patch @@ -0,0 +1,149 @@ +From 9af0214a2daf5a100ee12b231fed8bc5089cd70f Mon Sep 17 00:00:00 2001 +From: Shanker Donthineni shankerd@codeaurora.org +Date: Tue, 18 Oct 2016 20:57:36 -0500 +Subject: [PATCH] arm64: Workaround Falkor erratum E1003 + +On the Qualcomm Datacenter Technologies Falkor CPU, memory accesses may +allocate TLB entries using an incorrect ASID when TTBRx_EL1 is being +updated. Changing the TTBRx_EL1[ASID] and TTBRx_EL1[BADDR] fields +separately using a reserved ASID will ensure that there are no TLB entries +with incorrect ASID after changing the the ASID. + +Pseudo code: + write TTBRx_EL1[ASID] to a reserved value + ISB + write TTBRx_EL1[BADDR] to a desired value + ISB + write TTBRx_EL1[ASID] to a desired value + ISB + +Signed-off-by: Shanker Donthineni shankerd@codeaurora.org + +[Rebase from vanilla 4.5 onto CentOS 7.3 AltArch] +Signed-off-by: Christopher Covington cov@codeaurora.org +--- + arch/arm64/Kconfig | 11 +++++++++++ + arch/arm64/include/asm/cpufeature.h | 3 ++- + arch/arm64/kernel/cpu_errata.c | 7 +++++++ + arch/arm64/mm/context.c | 10 ++++++++++ + arch/arm64/mm/proc.S | 21 +++++++++++++++++++++ + 5 files changed, 51 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 465a423..e3ef1b1 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -478,6 +478,17 @@ config CAVIUM_ERRATUM_24575 + + If unsure, say Y. + ++config QCOM_FALKOR_ERRATUM_E1003 ++ bool "Falkor E1003: Incorrect translation due to ASID change" ++ default y ++ help ++ An incorrect translation TLBI entry may be created while ++ changing the ASID & translation table address together for ++ TTBR0_EL1. The workaround for this issue is use a reserved ++ ASID in cpu_do_switch_mm() before switching to target ASID. ++ ++ If unsure, say Y. ++ + endmenu + + +diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h +index ba93628..d8463e7 100644 +--- a/arch/arm64/include/asm/cpufeature.h ++++ b/arch/arm64/include/asm/cpufeature.h +@@ -36,8 +36,9 @@ + #define ARM64_HAS_VIRT_HOST_EXTN 11 + #define ARM64_WORKAROUND_CAVIUM_27456 12 + #define ARM64_WORKAROUND_CAVIUM_24575 13 ++#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 14 + +-#define ARM64_NCAPS 14 ++#define ARM64_NCAPS 15 + + #ifndef __ASSEMBLY__ + +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 89c13d7..a729969 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -105,6 +105,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + MIDR_RANGE(MIDR_THUNDERX, 0x00, 0x01), + }, + #endif ++#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1003 ++ { ++ .desc = "Qualcomm Falkor erratum E1003", ++ .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003, ++ MIDR_RANGE(MIDR_QCOM_FALKOR, 0x00, 0x00), ++ }, ++#endif + { + } + }; +diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c +index e87f53f..bdd9afd 100644 +--- a/arch/arm64/mm/context.c ++++ b/arch/arm64/mm/context.c +@@ -48,6 +48,11 @@ static void flush_context(unsigned int cpu) + /* Update the list of reserved ASIDs and the ASID bitmap. */ + bitmap_clear(asid_map, 0, NUM_USER_ASIDS); + ++ /* Reserve ASID '1' for Falkor erratum E1003 */ ++ if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_E1003) && ++ cpus_have_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003)) ++ __set_bit(1, asid_map); ++ + /* + * Ensure the generation bump is observed before we xchg the + * active_asids. +@@ -209,6 +214,11 @@ static int asids_init(void) + panic("Failed to allocate bitmap for %lu ASIDs\n", + NUM_USER_ASIDS); + ++ /* Reserve ASID '1' for Falkor erratum E1003 */ ++ if (IS_ENABLED(CONFIG_QCOM_FALKOR_ERRATUM_E1003) && ++ cpus_have_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003)) ++ __set_bit(1, asid_map); ++ + pr_info("ASID allocator initialised with %lu entries\n", NUM_USER_ASIDS); + return 0; + } +diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S +index dc470b0..e8f6a2a 100644 +--- a/arch/arm64/mm/proc.S ++++ b/arch/arm64/mm/proc.S +@@ -134,6 +134,27 @@ ENDPROC(cpu_do_resume) + ENTRY(cpu_do_switch_mm) + mmid x1, x1 // get mm->context.id + bfi x0, x1, #48, #16 // set the ASID ++#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1003 ++alternative_if_not ARM64_WORKAROUND_QCOM_FALKOR_E1003 ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++alternative_else ++ mrs x2, ttbr0_el1 // get cuurent TTBR0_EL1 ++ mov x3, #1 // reserved ASID ++ bfi x2, x3, #48, #16 // set the reserved ASID + old BADDR ++ msr ttbr0_el1, x2 // update TTBR0_EL1 ++ isb ++ bfi x2, x0, #0, #48 // set the desired BADDR + reserved ASID ++ msr ttbr0_el1, x2 // update TTBR0_EL1 ++ isb ++alternative_endif ++#endif + msr ttbr0_el1, x0 // set TTBR0 + isb + alternative_if_not ARM64_WORKAROUND_CAVIUM_27456 +-- +1.8.3.1 + diff --git a/SOURCES/4002-arm64-Workaround-Falkor-E1009.patch b/SOURCES/4002-arm64-Workaround-Falkor-E1009.patch new file mode 100644 index 0000000..03c9edb --- /dev/null +++ b/SOURCES/4002-arm64-Workaround-Falkor-E1009.patch @@ -0,0 +1,257 @@ +From 7aafd141f54cbbeafc71ed69ce5e053fa8ea2029 Mon Sep 17 00:00:00 2001 +From: Shanker Donthineni shankerd@codeaurora.org +Date: Tue, 18 Oct 2016 21:15:34 -0500 +Subject: [PATCH 3/3] arm64: Workaround Falkor E1009 + +During a TLB invalidate sequence targeting the inner shareable domain, +Falkor may prematurely complete the DSB before all loads and stores using +the old translation are observed; instruction fetches are not subject to +the conditions of this erratum. + +Signed-off-by: Shanker Donthineni shankerd@codeaurora.org + +[Rebase from vanilla 4.5 onto CentOS 7.3 AltArch] +Signed-off-by: Christopher Covington cov@codeaurora.org +--- + arch/arm64/Kconfig | 10 +++++++ + arch/arm64/include/asm/cpufeature.h | 3 ++- + arch/arm64/include/asm/tlbflush.h | 53 ++++++++++++++++++++++++++++++++++--- + arch/arm64/kernel/cpu_errata.c | 8 ++++++ + arch/arm64/kvm/hyp/tlb.c | 38 ++++++++++++++++++++++---- + 5 files changed, 102 insertions(+), 10 deletions(-) + +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 3cf1ea8..f811fd8 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -443,6 +443,16 @@ config QCOM_FALKOR_ERRATUM_E1003 + + If unsure, say Y. + ++config QCOM_FALKOR_ERRATUM_E1009 ++ bool "Falkor E1009: Prematurely complete a DSB after a TLBI" ++ default y ++ help ++ Falkor CPU may prematurely complete a DSB following a TLBI xxIS ++ invalidate maintenance operations. Repeat the TLBI operation one ++ more time to fix the issue. ++ ++ If unsure, say Y. ++ + endmenu + + +diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h +index 316e76b..fa1e759 100644 +--- a/arch/arm64/include/asm/cpufeature.h ++++ b/arch/arm64/include/asm/cpufeature.h +@@ -31,8 +31,9 @@ + #define ARM64_WORKAROUND_CAVIUM_27456 12 + #define ARM64_WORKAROUND_CAVIUM_24575 13 + #define ARM64_WORKAROUND_QCOM_FALKOR_E1003 14 ++#define ARM64_WORKAROUND_QCOM_FALKOR_E1009 15 + +-#define ARM64_NCAPS 15 ++#define ARM64_NCAPS 16 + + #ifndef __ASSEMBLY__ + +diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h +index b460ae2..51d68c1 100644 +--- a/arch/arm64/include/asm/tlbflush.h ++++ b/arch/arm64/include/asm/tlbflush.h +@@ -23,6 +23,8 @@ + + #include <linux/sched.h> + #include <asm/cputype.h> ++#include <asm/alternative.h> ++#include <asm/cpufeature.h> + + /* + * TLB Management +@@ -74,7 +76,14 @@ static inline void local_flush_tlb_all(void) + static inline void flush_tlb_all(void) + { + dsb(ishst); +- asm("tlbi vmalle1is"); ++ asm volatile("tlbi vmalle1is \n" ++ ALTERNATIVE( ++ "nop \n" ++ "nop \n", ++ "dsb ish \n" ++ "tlbi vmalle1is \n", ++ ARM64_WORKAROUND_QCOM_FALKOR_E1009) ++ : :); + dsb(ish); + isb(); + } +@@ -84,7 +93,14 @@ static inline void flush_tlb_mm(struct mm_struct *mm) + unsigned long asid = ASID(mm) << 48; + + dsb(ishst); +- asm("tlbi aside1is, %0" : : "r" (asid)); ++ asm volatile("tlbi aside1is, %0 \n" ++ ALTERNATIVE( ++ "nop \n" ++ "nop \n", ++ "dsb ish \n" ++ "tlbi aside1is, %0 \n", ++ ARM64_WORKAROUND_QCOM_FALKOR_E1009) ++ : : "r" (asid)); + dsb(ish); + } + +@@ -94,7 +110,14 @@ static inline void flush_tlb_page(struct vm_area_struct *vma, + unsigned long addr = uaddr >> 12 | (ASID(vma->vm_mm) << 48); + + dsb(ishst); +- asm("tlbi vale1is, %0" : : "r" (addr)); ++ asm volatile("tlbi vale1is, %0 \n" ++ ALTERNATIVE( ++ "nop \n" ++ "nop \n", ++ "dsb ish \n" ++ "tlbi vale1is, %0 \n", ++ ARM64_WORKAROUND_QCOM_FALKOR_E1009) ++ : : "r" (addr)); + dsb(ish); + } + +@@ -126,6 +149,13 @@ static inline void __flush_tlb_range(struct vm_area_struct *vma, + else + asm("tlbi vae1is, %0" : : "r"(addr)); + } ++ asm volatile(ALTERNATIVE( ++ "nop \n" ++ "nop \n", ++ "dsb ish \n" ++ "tlbi vae1is, %0 \n", ++ ARM64_WORKAROUND_QCOM_FALKOR_E1009) ++ : : "r" (end)); + dsb(ish); + } + +@@ -150,6 +180,14 @@ static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end + dsb(ishst); + for (addr = start; addr < end; addr += 1 << (PAGE_SHIFT - 12)) + asm("tlbi vaae1is, %0" : : "r"(addr)); ++ ++ asm volatile(ALTERNATIVE( ++ "nop \n" ++ "nop \n", ++ "dsb ish \n" ++ "tlbi vaae1is, %0 \n", ++ ARM64_WORKAROUND_QCOM_FALKOR_E1009) ++ : : "r" (end)); + dsb(ish); + isb(); + } +@@ -163,7 +201,14 @@ static inline void __flush_tlb_pgtable(struct mm_struct *mm, + { + unsigned long addr = uaddr >> 12 | (ASID(mm) << 48); + +- asm("tlbi vae1is, %0" : : "r" (addr)); ++ asm volatile("tlbi vae1is, %0 \n" ++ ALTERNATIVE( ++ "nop \n" ++ "nop \n", ++ "dsb ish \n" ++ "tlbi vae1is, %0 \n", ++ ARM64_WORKAROUND_QCOM_FALKOR_E1009) ++ : : "r" (addr)); + dsb(ish); + } + +diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c +index 0373999..a38b1e5 100644 +--- a/arch/arm64/kernel/cpu_errata.c ++++ b/arch/arm64/kernel/cpu_errata.c +@@ -108,6 +108,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = { + MIDR_RANGE(MIDR_QCOM_FALKOR, 0x00, 0x00), + }, + #endif ++#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1009 ++ { ++ .desc = "Qualcomm Falkor erratum E1009", ++ .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1009, ++ MIDR_RANGE(MIDR_QCOM_FALKOR, 0x00, 0x00), ++ }, ++#endif ++ + { + } + }; +diff --git a/arch/arm64/kvm/hyp/tlb.c b/arch/arm64/kvm/hyp/tlb.c +index 2a7e0d8..362cec4 100644 +--- a/arch/arm64/kvm/hyp/tlb.c ++++ b/arch/arm64/kvm/hyp/tlb.c +@@ -32,7 +32,14 @@ static void __hyp_text __tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) + * whole of Stage-1. Weep... + */ + ipa >>= 12; +- asm volatile("tlbi ipas2e1is, %0" : : "r" (ipa)); ++ asm volatile("tlbi ipas2e1is, %0 \n" ++ ALTERNATIVE( ++ "nop \n" ++ "nop \n", ++ "dsb ish \n" ++ "tlbi ipas2e1is, %0 \n", ++ ARM64_WORKAROUND_QCOM_FALKOR_E1009) ++ : : "r" (ipa)); + + /* + * We have to ensure completion of the invalidation at Stage-2, +@@ -41,7 +48,14 @@ static void __hyp_text __tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa) + * the Stage-1 invalidation happened first. + */ + dsb(ish); +- asm volatile("tlbi vmalle1is" : : ); ++ asm volatile("tlbi vmalle1is \n" ++ ALTERNATIVE( ++ "nop \n" ++ "nop \n", ++ "dsb ish \n" ++ "tlbi vmalle1is \n", ++ ARM64_WORKAROUND_QCOM_FALKOR_E1009) ++ : : ); + dsb(ish); + isb(); + +@@ -60,7 +74,14 @@ static void __hyp_text __tlb_flush_vmid(struct kvm *kvm) + write_sysreg(kvm->arch.vttbr, vttbr_el2); + isb(); + +- asm volatile("tlbi vmalls12e1is" : : ); ++ asm volatile("tlbi vmalls12e1is \n" ++ ALTERNATIVE( ++ "nop \n" ++ "nop \n", ++ "dsb ish \n" ++ "tlbi vmalls12e1is \n", ++ ARM64_WORKAROUND_QCOM_FALKOR_E1009) ++ : : ); + dsb(ish); + isb(); + +@@ -72,8 +93,15 @@ __alias(__tlb_flush_vmid) void __kvm_tlb_flush_vmid(struct kvm *kvm); + static void __hyp_text __tlb_flush_vm_context(void) + { + dsb(ishst); +- asm volatile("tlbi alle1is \n" +- "ic ialluis ": : ); ++ asm volatile("tlbi alle1is \n" ++ ALTERNATIVE( ++ "nop \n" ++ "nop \n", ++ "dsb ish \n" ++ "tlbi alle1is \n", ++ ARM64_WORKAROUND_QCOM_FALKOR_E1009) ++ "ic ialluis \n" ++ : : ); + dsb(ish); + } + +-- +Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc. +Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. + diff --git a/SOURCES/config-centos-sig b/SOURCES/config-centos-sig index 3f73759..1051e4b 100644 --- a/SOURCES/config-centos-sig +++ b/SOURCES/config-centos-sig @@ -1,2 +1,5 @@ # This file is for SIG members to add additional configuration options # common to CentOS SIGs but not configured in other config files + +CONFIG_QCOM_FALKOR_ERRATUM_E1003=y +CONFIG_QCOM_FALKOR_ERRATUM_E1009=y diff --git a/SPECS/kernel-aarch64.spec b/SPECS/kernel-aarch64.spec index e7af8ae..ffaafe7 100644 --- a/SPECS/kernel-aarch64.spec +++ b/SPECS/kernel-aarch64.spec @@ -12,7 +12,7 @@ Summary: The Linux kernel
%define rpmversion 4.5.0 %define pkgrelease 15.el7 -%define centupdate 15.el7 +%define centupdate 16.el7
# allow pkg_release to have configurable %{?dist} tag %define specrelease %%SPECRELEASE%% @@ -324,6 +324,11 @@ Source58: config-generic Source59: config-debug Source60: config-centos-sig
+# QDF2400 Patches +Patch4000: 4000-arm64-Define-Qualcomm-Technologies-ARMv8-CPU.patch +Patch4001: 4001-arm64-Workaround-Falkor-E1003.patch +Patch4002: 4002-arm64-Workaround-Falkor-E1009.patch + # empty final patch to facilitate testing of kernel patches Patch999999: linux-kernel-test.patch
@@ -652,6 +657,11 @@ if [ ! -d .git ]; then git commit -a -q -m "baseline" fi
+# Apply QDF2400 patches +git am %{PATCH4000} +git am %{PATCH4001} +git am %{PATCH4002} + # Any further pre-build tree manipulations happen here.
chmod +x scripts/checkpatch.pl @@ -1424,6 +1434,9 @@ fi %kernel_variant_files %{with_debug} kernel-debug debug
%changelog +* Mon Nov 07 2016 Christopher Covington cov@codeaurora.org [4.5.0-16.el7] +- Add git machinery (Jim Perrin) + * Wed Oct 12 2016 Mark Langsdorf mlangsdo@redhat.com [4.5.0-15.el7] - [redhat] configs: disable CPPC (Mark Langsdorf) [1382023]