Signed-off-by: Duc Dang dhdang@apm.com --- ...ix-GIC-irq-model-default-PCI-IRQ-polarity.patch | 83 ++++++++++++++++++++++ SPECS/kernel-aarch64.spec | 3 + 2 files changed, 86 insertions(+) create mode 100644 SOURCES/1018-ACPI-PCI-fix-GIC-irq-model-default-PCI-IRQ-polarity.patch
diff --git a/SOURCES/1018-ACPI-PCI-fix-GIC-irq-model-default-PCI-IRQ-polarity.patch b/SOURCES/1018-ACPI-PCI-fix-GIC-irq-model-default-PCI-IRQ-polarity.patch new file mode 100644 index 0000000..22ebebe --- /dev/null +++ b/SOURCES/1018-ACPI-PCI-fix-GIC-irq-model-default-PCI-IRQ-polarity.patch @@ -0,0 +1,83 @@ +From 40cbfb67ef9e9f8dc1813447aebb860572a8d414 Mon Sep 17 00:00:00 2001 +From: Lorenzo Pieralisi lorenzo.pieralisi@arm.com +Date: Mon, 5 Sep 2016 15:12:38 +0100 +Subject: [PATCH 1018/1018] ACPI / PCI: fix GIC irq model default PCI IRQ + polarity + +On ACPI ARM based systems the GIC interrupt controller +and corresponding interrupt model permit only the high +polarity for level interrupts. + +ACPI firmware describes PCI legacy IRQs through entries +in the _PRT objects. Entries in the _PRT can be of two types: + +- Static: not configurable, trigger/polarity default to level-low, + _PRT entry defines the global GSI interrupt number +- Configurable: _PRT interrupt entry contains a reference to the + corresponding PCI interrupt link device (that in turn provides the + interrupt descriptor through its _CRS/_PRS methods) + +Configurable IRQ entries are not currently allowed by the ACPI +specification on ARM since they can only be used for interrupt pins that +are routable, as per ACPI specifications (version 6.1, 6.2.13): + +"[...] There are two ways that _PRT can be used. Typically, the +interrupt input that a given PCI interrupt is on is configurable. For +example, a given PCI interrupt might be configured for either IRQ 10 or +11 on an 8259 interrupt controller. In this model, each interrupt is +represented in the ACPI namespace as a PCI Interrupt Link Device. [...]" + +ARM platforms GIC configurations do not allow dynamic IRQ routing, +since routing is statically laid out at synthesis time; therefore PCI +interrupt links cannot be used for PCI legacy IRQ descriptions in the +_PRT on ARM systems. + +On the other hand, current core ACPI code handling PCI legacy IRQs +consider IRQ trigger/polarity for static _PRT entries as level-low. + +On ARM systems with a GIC interrupt controller and corresponding +ACPI interrupt model this does not work in that GIC interrupt +controller is only capable of handling level interrupts whose +polarity is high (for PCI legacy IRQs - that are level-low by +specification - this means that the legacy IRQs are inverted before +reaching the interrupt controller pin), resulting in IRQ allocation +failures such as: + +genirq: Setting trigger mode 8 for irq 18 failed (gic_set_type+0x0/0x48) + +Change the default polarity for PCI legacy IRQs to high on systems +booting wth ACPI on platforms with a GIC interrupt controller model, +fixing the discrepancy between specification and HW behaviour. + +Signed-off-by: Lorenzo Pieralisi lorenzo.pieralisi@arm.com +Acked-by: Marc Zyngier marc.zyngier@arm.com +Tested-by: Duc Dang dhdang@apm.com +Signed-off-by: Rafael J. Wysocki rafael.j.wysocki@intel.com +--- + drivers/acpi/pci_irq.c | 10 +++++++++- + 1 file changed, 9 insertions(+), 1 deletion(-) + +diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c +index c8e169e..a40b8dd 100644 +--- a/drivers/acpi/pci_irq.c ++++ b/drivers/acpi/pci_irq.c +@@ -393,7 +393,15 @@ int acpi_pci_irq_enable(struct pci_dev *dev) + int gsi; + u8 pin; + int triggering = ACPI_LEVEL_SENSITIVE; +- int polarity = ACPI_ACTIVE_LOW; ++ /* ++ * On ARM systems with the GIC interrupt model, level interrupts ++ * are always polarity high by specification; PCI legacy ++ * IRQs lines are inverted before reaching the interrupt ++ * controller and must therefore be considered active high ++ * as default. ++ */ ++ int polarity = acpi_irq_model == ACPI_IRQ_MODEL_GIC ? ++ ACPI_ACTIVE_HIGH : ACPI_ACTIVE_LOW; + char *link = NULL; + char link_desc[16]; + int rc; +-- +1.8.3.1 + diff --git a/SPECS/kernel-aarch64.spec b/SPECS/kernel-aarch64.spec index c44bdc7..4c20b21 100644 --- a/SPECS/kernel-aarch64.spec +++ b/SPECS/kernel-aarch64.spec @@ -342,6 +342,7 @@ Patch1014: 1014-drivers-net-xgene-Fix-MSS-programming.patch Patch1015: 1015-drivers-net-xgene-fix-Use-GPIO-to-get-link-status.patch Patch1016: 1016-drivers-net-xgene-fix-Disable-coalescing-on-v1-hardw.patch Patch1017: 1017-drivers-net-xgene-fix-Coalescing-values-for-v2-hardw.patch +Patch1018: 1018-ACPI-PCI-fix-GIC-irq-model-default-PCI-IRQ-polarity.patch
# QDF2400 Patches Patch4000: 4000-arm64-Define-Qualcomm-Technologies-ARMv8-CPU.patch @@ -694,6 +695,7 @@ git am %{PATCH1014} git am %{PATCH1015} git am %{PATCH1016} git am %{PATCH1017} +git am %{PATCH1018}
# Apply QDF2400 patches git am %{PATCH4000} @@ -1473,6 +1475,7 @@ fi
%changelog * Thu Nov 10 2016 Duc Dang dhdang@apm.com [4.5.0-17.el7] +- Integrate upstream fix for GIC default PCI IRQ polarity - Integrate upstream updates for X-Gene Enet driver - Avoid dma_buffer overrun for SlimPRO I2C driver - Add X-Gene SoC PMU support