From: David Daney david.daney@cavium.com

Signed-off-by: David Daney david.daney@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/irqchip/irq-gic-v3-its.c | 14 +++++++++++++- include/linux/irqchip/arm-gic-v3.h | 2 ++ 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index c00e2db..83204f4 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1225,11 +1225,23 @@ static int its_pci_msi_vec_count(struct pci_dev *pdev) return max(msi, msix); }

+static u32 its_dflt_pci_requester_id(struct pci_dev *pdev, u16 alias) +{ + return alias; +} + +static its_pci_requester_id_t its_pci_requester_id = its_dflt_pci_requester_id; +void set_its_pci_requester_id(its_pci_requester_id_t fn) +{ + its_pci_requester_id = fn; +} +EXPORT_SYMBOL(set_its_pci_requester_id); + static int its_get_pci_alias(struct pci_dev *pdev, u16 alias, void *data) { struct its_pci_alias *dev_alias = data;

- dev_alias->dev_id = alias; + dev_alias->dev_id = its_pci_requester_id(pdev, alias); if (pdev != dev_alias->pdev) dev_alias->count += its_pci_msi_vec_count(dev_alias->pdev);

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index ffbc034..18e3757 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -389,6 +389,8 @@ int its_cpu_init(void); int its_init(struct device_node *node, struct rdists *rdists, struct irq_domain *domain);

+typedef u32 (*its_pci_requester_id_t)(struct pci_dev *, u16); +void set_its_pci_requester_id(its_pci_requester_id_t fn); #endif

#endif

From: David Daney david.daney@cavium.com

Needed to map SPI interrupt sources.

Signed-off-by: David Daney david.daney@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/irqchip/irq-gic-v3.c | 5 +++++ include/linux/irqchip/arm-gic-v3.h | 1 + 2 files changed, 6 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index c52f7ba..0019fed 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -58,6 +58,11 @@ static struct gic_chip_data gic_data __read_mostly; /* Our default, arbitrary priority value. Linux only uses one anyway. */ #define DEFAULT_PMR_VALUE 0xf0

+struct irq_domain *gic_get_irq_domain(void) +{ + return gic_data.domain; +} + static inline unsigned int gic_irq(struct irq_data *d) { return d->hwirq; diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 18e3757..5992224 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -391,6 +391,7 @@ int its_init(struct device_node *node, struct rdists *rdists,

typedef u32 (*its_pci_requester_id_t)(struct pci_dev *, u16); void set_its_pci_requester_id(its_pci_requester_id_t fn); +struct irq_domain *gic_get_irq_domain(void); #endif

#endif

From: Robert Richter rrichter@cavium.com

This reverts commit 22b25883dd8632f5f84bc627eeb9ca81ee8f6377.

Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/pci/host/pcie-thunder.c | 88 ----------------------------------------- 1 file changed, 88 deletions(-)

diff --git a/drivers/pci/host/pcie-thunder.c b/drivers/pci/host/pcie-thunder.c index cbe4b44..7428401 100644 --- a/drivers/pci/host/pcie-thunder.c +++ b/drivers/pci/host/pcie-thunder.c @@ -329,94 +329,6 @@ static struct platform_driver thunder_pcie_driver = { }; module_platform_driver(thunder_pcie_driver);

-#ifdef CONFIG_ACPI - -static int -thunder_mmcfg_read_config(struct pci_mmcfg_region *cfg, unsigned int busnr, - unsigned int devfn, int reg, int len, u32 *value) -{ - struct thunder_pcie *pcie = cfg->data; - void __iomem *addr; - - if (!pcie->valid) { - /* Not support for now */ - pr_err("RC PEM not supported !!!\n"); - return PCIBIOS_DEVICE_NOT_FOUND; - } - - addr = thunder_pcie_get_cfg_addr(pcie, busnr, devfn, reg); - - switch (len) { - case 1: - *value = readb(addr); - break; - case 2: - *value = readw(addr); - break; - case 4: - *value = readl(addr); - break; - default: - return PCIBIOS_BAD_REGISTER_NUMBER; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int thunder_mmcfg_write_config(struct pci_mmcfg_region *cfg, - unsigned int busnr, unsigned int devfn, int reg, int len, - u32 value) { - struct thunder_pcie *pcie = cfg->data; - void __iomem *addr; - - if (!pcie->valid) { - /* Not support for now */ - pr_err("RC PEM not supported !!!\n"); - return PCIBIOS_DEVICE_NOT_FOUND; - } - - addr = thunder_pcie_get_cfg_addr(pcie, busnr, devfn, reg); - - switch (len) { - case 1: - writeb(value, addr); - break; - case 2: - writew(value, addr); - break; - case 4: - writel(value, addr); - break; - default: - return PCIBIOS_BAD_REGISTER_NUMBER; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int thunder_acpi_mcfg_fixup(struct acpi_pci_root *root, - struct pci_mmcfg_region *cfg) -{ - struct thunder_pcie *pcie; - - pcie = kzalloc(sizeof(*pcie), GFP_KERNEL); - if (!pcie) - return -ENOMEM; - - pcie->dev = &root->device->dev; - - thunder_pcie_config(pcie, cfg->address); - - pcie->cfg_base = cfg->virt; - cfg->data = pcie; - cfg->read = thunder_mmcfg_read_config; - cfg->write = thunder_mmcfg_write_config; - - return 0; -} -DECLARE_ACPI_MCFG_FIXUP("CAVIUM", "THUNDERX", thunder_acpi_mcfg_fixup); -#endif - MODULE_AUTHOR("Sunil Goutham"); MODULE_DESCRIPTION("Cavium Thunder ECAM host controller driver"); MODULE_LICENSE("GPL v2");

From: Sunil Goutham sgoutham@cavium.com

Adding support for receive hashing HW offload by using RSS_ALG and RSS_TAG fields of CQE_RX descriptor. Also removed dependency on minimum receive queue count to configure RSS so that hash is always generated.

This hash is used by RPS logic to distribute flows across multiple CPUs. Offload can be disabled via ethtool.

Signed-off-by: Sunil Goutham sgoutham@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- .../net/ethernet/cavium/thunder/nicvf_ethtool.c | 7 ++--- drivers/net/ethernet/cavium/thunder/nicvf_main.c | 36 +++++++++++++++++++++- 2 files changed, 38 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c b/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c index 1c7a98f..1c606e7 100644 --- a/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c +++ b/drivers/net/ethernet/cavium/thunder/nicvf_ethtool.c @@ -504,13 +504,12 @@ static int nicvf_set_rxfh(struct net_device *dev, const u32 *indir, if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP) return -EOPNOTSUPP;

- if ((nic->qs->rq_cnt <= 1) || (nic->cpi_alg != CPI_ALG_NONE)) { - rss->enable = false; - rss->hash_bits = 0; + if (!rss->enable) { + netdev_err(nic->netdev, + "RSS is disabled, cannot change settings\n"); return -EIO; }

- rss->enable = true; if (indir) { for (idx = 0; idx < rss->rss_size; idx++) rss->ind_tbl[idx] = indir[idx]; diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_main.c b/drivers/net/ethernet/cavium/thunder/nicvf_main.c index 3b90afb..76c6c52 100644 --- a/drivers/net/ethernet/cavium/thunder/nicvf_main.c +++ b/drivers/net/ethernet/cavium/thunder/nicvf_main.c @@ -326,7 +326,7 @@ static int nicvf_rss_init(struct nicvf *nic)

nicvf_get_rss_size(nic);

- if ((nic->qs->rq_cnt <= 1) || (cpi_alg != CPI_ALG_NONE)) { + if (cpi_alg != CPI_ALG_NONE) { rss->enable = false; rss->hash_bits = 0; return 0; @@ -429,6 +429,34 @@ static void nicvf_snd_pkt_handler(struct net_device *netdev, } }

+static inline void nicvf_set_rxhash(struct net_device *netdev, + struct cqe_rx_t *cqe_rx, + struct sk_buff *skb) +{ + u8 hash_type; + u32 hash; + + if (!(netdev->features & NETIF_F_RXHASH)) + return; + + switch (cqe_rx->rss_alg) { + case RSS_ALG_TCP_IP: + case RSS_ALG_UDP_IP: + hash_type = PKT_HASH_TYPE_L4; + hash = cqe_rx->rss_tag; + break; + case RSS_ALG_IP: + hash_type = PKT_HASH_TYPE_L3; + hash = cqe_rx->rss_tag; + break; + default: + hash_type = PKT_HASH_TYPE_NONE; + hash = 0; + } + + skb_set_hash(skb, hash, hash_type); +} + static void nicvf_rcv_pkt_handler(struct net_device *netdev, struct napi_struct *napi, struct cmp_queue *cq, @@ -458,6 +486,8 @@ static void nicvf_rcv_pkt_handler(struct net_device *netdev,

nicvf_set_rx_frame_cnt(nic, skb);

+ nicvf_set_rxhash(netdev, cqe_rx, skb); + skb_record_rx_queue(skb, cqe_rx->rq_idx); if (netdev->hw_features & NETIF_F_RXCSUM) { /* HW by default verifies TCP/UDP/SCTP checksums */ @@ -1291,6 +1321,10 @@ static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)

netdev->features |= (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO | NETIF_F_GRO); +#ifdef VNIC_RSS_SUPPORT + netdev->features |= NETIF_F_RXHASH; +#endif + netdev->hw_features = netdev->features;

netdev->netdev_ops = &nicvf_netdev_ops;

From: Robert Richter rrichter@cavium.com

We need code separation for later acpi integration.

Originally based on a patch from: Tomasz Nowicki tomasz.nowicki@linaro.org

Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 48 +++++++++++++++++------ 1 file changed, 35 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c index b961a89..615b2af 100644 --- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c @@ -835,18 +835,28 @@ static void bgx_get_qlm_mode(struct bgx *bgx) } }

-static void bgx_init_of(struct bgx *bgx, struct device_node *np) +#if IS_ENABLED(CONFIG_OF_MDIO) + +static int bgx_init_of_phy(struct bgx *bgx) { + struct device_node *np; struct device_node *np_child; u8 lmac = 0; + char bgx_sel[5]; + const char *mac;

- for_each_child_of_node(np, np_child) { - struct device_node *phy_np; - const char *mac; + /* Get BGX node from DT */ + snprintf(bgx_sel, 5, "bgx%d", bgx->bgx_id); + np = of_find_node_by_name(NULL, bgx_sel); + if (!np) + return -ENODEV;

- phy_np = of_parse_phandle(np_child, "phy-handle", 0); - if (phy_np) - bgx->lmac[lmac].phydev = of_phy_find_device(phy_np); + for_each_child_of_node(np, np_child) { + struct device_node *phy_np = of_parse_phandle(np_child, + "phy-handle", 0); + if (!phy_np) + continue; + bgx->lmac[lmac].phydev = of_phy_find_device(phy_np);

mac = of_get_mac_address(np_child); if (mac) @@ -858,6 +868,21 @@ static void bgx_init_of(struct bgx *bgx, struct device_node *np) if (lmac == MAX_LMAC_PER_BGX) break; } + return 0; +} + +#else + +static int bgx_init_of_phy(struct bgx *bgx) +{ + return -ENODEV; +} + +#endif /* CONFIG_OF_MDIO */ + +static int bgx_init_phy(struct bgx *bgx) +{ + return bgx_init_of_phy(bgx); }

static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -865,8 +890,6 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) int err; struct device *dev = &pdev->dev; struct bgx *bgx = NULL; - struct device_node *np; - char bgx_sel[5]; u8 lmac;

bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL); @@ -902,10 +925,9 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) bgx_vnic[bgx->bgx_id] = bgx; bgx_get_qlm_mode(bgx);

- snprintf(bgx_sel, 5, "bgx%d", bgx->bgx_id); - np = of_find_node_by_name(NULL, bgx_sel); - if (np) - bgx_init_of(bgx, np); + err = bgx_init_phy(bgx); + if (err) + goto err_enable;

bgx_init_hw(bgx);

From: Radha Mohan Chintakuntla rchintakuntla@cavium.com

This patch fixes a possible crash in the octeon_mdiobus_probe function if the return values are not handled properly.

Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/net/phy/mdio-octeon.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c index 507aade..428ae75 100644 --- a/drivers/net/phy/mdio-octeon.c +++ b/drivers/net/phy/mdio-octeon.c @@ -277,24 +277,28 @@ static int octeon_mdiobus_probe(struct platform_device *pdev) return -ENOMEM;

res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res_mem == NULL) { dev_err(&pdev->dev, "found no memory resource\n"); - err = -ENXIO; - goto fail; + return -ENXIO; } + bus->mdio_phys = res_mem->start; bus->regsize = resource_size(res_mem); + if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize, res_mem->name)) { dev_err(&pdev->dev, "request_mem_region failed\n"); - goto fail; + return -ENXIO; } + bus->register_base = (u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize); + if (!bus->register_base) { + dev_err(&pdev->dev, "dev_ioremap failed\n"); + return -ENOMEM; + }

bus->mii_bus = mdiobus_alloc(); - if (!bus->mii_bus) goto fail;

From: David Daney david.daney@cavium.com

The dma_alloc_coherent() function returns a virtual address which can be used for coherent access to the underlying memory. On some architectures, like arm64, undefined behavior results if this memory is also accessed via virtual mappings that are not coherent. Because of their undefined nature, operations like virt_to_page() return garbage when passed virtual addresses obtained from dma_alloc_coherent(). Any subsequent mappings via vmap() of the garbage page values are unusable and result in bad things like bus errors (synchronous aborts in ARM64 speak).

The MLX4 driver contains code that does the equivalent of:

vmap(virt_to_page(dma_alloc_coherent))

This results in an OOPs when the device is opened.

To fix this...

Always use result of dma_alloc_coherent() directly.

Remove 'max_direct' parameter to mlx4_buf_alloc(), as it is unused, and adjust all callers.

Remove mlx4_en_map_buffer() and mlx4_en_unmap_buffer() as they now do nothing, and adjust all callers.

Remove 'page_list' element from struct mlx4_buf as it is unused.

Signed-off-by: David Daney david.daney@cavium.com Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/infiniband/hw/mlx4/cq.c | 2 +- drivers/infiniband/hw/mlx4/qp.c | 2 +- drivers/infiniband/hw/mlx4/srq.c | 3 +- drivers/net/ethernet/mellanox/mlx4/alloc.c | 104 +++++----------------- drivers/net/ethernet/mellanox/mlx4/en_cq.c | 9 +- drivers/net/ethernet/mellanox/mlx4/en_netdev.c | 2 +- drivers/net/ethernet/mellanox/mlx4/en_resources.c | 32 ------- drivers/net/ethernet/mellanox/mlx4/en_rx.c | 11 +-- drivers/net/ethernet/mellanox/mlx4/en_tx.c | 14 +-- drivers/net/ethernet/mellanox/mlx4/mlx4_en.h | 2 - drivers/net/ethernet/mellanox/mlx4/mr.c | 5 +- include/linux/mlx4/device.h | 11 +-- 12 files changed, 33 insertions(+), 164 deletions(-)

diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c index 36eb3d0..25e5aa5 100644 --- a/drivers/infiniband/hw/mlx4/cq.c +++ b/drivers/infiniband/hw/mlx4/cq.c @@ -102,7 +102,7 @@ static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf * int err;

err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size, - PAGE_SIZE * 2, &buf->buf, GFP_KERNEL); + &buf->buf, GFP_KERNEL);

if (err) goto out; diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c index c5a3a5f..baf9e11 100644 --- a/drivers/infiniband/hw/mlx4/qp.c +++ b/drivers/infiniband/hw/mlx4/qp.c @@ -772,7 +772,7 @@ static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd, *qp->db.db = 0; }

- if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2, &qp->buf, gfp)) { + if (mlx4_buf_alloc(dev->dev, qp->buf_size, &qp->buf, gfp)) { err = -ENOMEM; goto err_db; } diff --git a/drivers/infiniband/hw/mlx4/srq.c b/drivers/infiniband/hw/mlx4/srq.c index dce5dfe..121730b 100644 --- a/drivers/infiniband/hw/mlx4/srq.c +++ b/drivers/infiniband/hw/mlx4/srq.c @@ -140,8 +140,7 @@ struct ib_srq *mlx4_ib_create_srq(struct ib_pd *pd,

*srq->db.db = 0;

- if (mlx4_buf_alloc(dev->dev, buf_size, PAGE_SIZE * 2, &srq->buf, - GFP_KERNEL)) { + if (mlx4_buf_alloc(dev->dev, buf_size, &srq->buf, GFP_KERNEL)) { err = -ENOMEM; goto err_db; } diff --git a/drivers/net/ethernet/mellanox/mlx4/alloc.c b/drivers/net/ethernet/mellanox/mlx4/alloc.c index 0c51c69..db6ba3e 100644 --- a/drivers/net/ethernet/mellanox/mlx4/alloc.c +++ b/drivers/net/ethernet/mellanox/mlx4/alloc.c @@ -576,103 +576,41 @@ out:

return res; } -/* - * Handling for queue buffers -- we allocate a bunch of memory and - * register it in a memory region at HCA virtual address 0. If the - * requested size is > max_direct, we split the allocation into - * multiple pages, so we don't require too much contiguous memory. + +/* Handling for queue buffers -- we allocate a bunch of memory and + * register it in a memory region at HCA virtual address 0. */

-int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, +int mlx4_buf_alloc(struct mlx4_dev *dev, int size, struct mlx4_buf *buf, gfp_t gfp) { dma_addr_t t;

- if (size <= max_direct) { - buf->nbufs = 1; - buf->npages = 1; - buf->page_shift = get_order(size) + PAGE_SHIFT; - buf->direct.buf = dma_alloc_coherent(&dev->persist->pdev->dev, - size, &t, gfp); - if (!buf->direct.buf) - return -ENOMEM; - - buf->direct.map = t; - - while (t & ((1 << buf->page_shift) - 1)) { - --buf->page_shift; - buf->npages *= 2; - } + buf->nbufs = 1; + buf->npages = 1; + buf->page_shift = get_order(size) + PAGE_SHIFT; + buf->direct.buf = dma_alloc_coherent(&dev->persist->pdev->dev, + size, &t, gfp); + if (!buf->direct.buf) + return -ENOMEM;

- memset(buf->direct.buf, 0, size); - } else { - int i; - - buf->direct.buf = NULL; - buf->nbufs = (size + PAGE_SIZE - 1) / PAGE_SIZE; - buf->npages = buf->nbufs; - buf->page_shift = PAGE_SHIFT; - buf->page_list = kcalloc(buf->nbufs, sizeof(*buf->page_list), - gfp); - if (!buf->page_list) - return -ENOMEM; - - for (i = 0; i < buf->nbufs; ++i) { - buf->page_list[i].buf = - dma_alloc_coherent(&dev->persist->pdev->dev, - PAGE_SIZE, - &t, gfp); - if (!buf->page_list[i].buf) - goto err_free; - - buf->page_list[i].map = t; - - memset(buf->page_list[i].buf, 0, PAGE_SIZE); - } + buf->direct.map = t;

- if (BITS_PER_LONG == 64) { - struct page **pages; - pages = kmalloc(sizeof *pages * buf->nbufs, gfp); - if (!pages) - goto err_free; - for (i = 0; i < buf->nbufs; ++i) - pages[i] = virt_to_page(buf->page_list[i].buf); - buf->direct.buf = vmap(pages, buf->nbufs, VM_MAP, PAGE_KERNEL); - kfree(pages); - if (!buf->direct.buf) - goto err_free; - } + while (t & ((1 << buf->page_shift) - 1)) { + --buf->page_shift; + buf->npages *= 2; }

- return 0; - -err_free: - mlx4_buf_free(dev, size, buf); + memset(buf->direct.buf, 0, size);

- return -ENOMEM; + return 0; } EXPORT_SYMBOL_GPL(mlx4_buf_alloc);

void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf) { - int i; - - if (buf->nbufs == 1) - dma_free_coherent(&dev->persist->pdev->dev, size, - buf->direct.buf, - buf->direct.map); - else { - if (BITS_PER_LONG == 64) - vunmap(buf->direct.buf); - - for (i = 0; i < buf->nbufs; ++i) - if (buf->page_list[i].buf) - dma_free_coherent(&dev->persist->pdev->dev, - PAGE_SIZE, - buf->page_list[i].buf, - buf->page_list[i].map); - kfree(buf->page_list); - } + dma_free_coherent(&dev->persist->pdev->dev, size, + buf->direct.buf, buf->direct.map); } EXPORT_SYMBOL_GPL(mlx4_buf_free);

@@ -789,7 +727,7 @@ void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db) EXPORT_SYMBOL_GPL(mlx4_db_free);

int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, - int size, int max_direct) + int size) { int err;

@@ -799,7 +737,7 @@ int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,

*wqres->db.db = 0;

- err = mlx4_buf_alloc(dev, size, max_direct, &wqres->buf, GFP_KERNEL); + err = mlx4_buf_alloc(dev, size, &wqres->buf, GFP_KERNEL); if (err) goto err_db;

diff --git a/drivers/net/ethernet/mellanox/mlx4/en_cq.c b/drivers/net/ethernet/mellanox/mlx4/en_cq.c index 63769df..fa0e0b1 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_cq.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_cq.c @@ -73,22 +73,16 @@ int mlx4_en_create_cq(struct mlx4_en_priv *priv, */ set_dev_node(&mdev->dev->persist->pdev->dev, node); err = mlx4_alloc_hwq_res(mdev->dev, &cq->wqres, - cq->buf_size, 2 * PAGE_SIZE); + cq->buf_size); set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); if (err) goto err_cq;

- err = mlx4_en_map_buffer(&cq->wqres.buf); - if (err) - goto err_res; - cq->buf = (struct mlx4_cqe *)cq->wqres.buf.direct.buf; *pcq = cq;

return 0;

-err_res: - mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size); err_cq: kfree(cq); *pcq = NULL; @@ -180,7 +174,6 @@ void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq **pcq) struct mlx4_en_dev *mdev = priv->mdev; struct mlx4_en_cq *cq = *pcq;

- mlx4_en_unmap_buffer(&cq->wqres.buf); mlx4_free_hwq_res(mdev->dev, &cq->wqres, cq->buf_size); if (mlx4_is_eq_vector_valid(mdev->dev, priv->port, cq->vector) && cq->is_tx == RX) diff --git a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c index e0de2fd..e2a489c 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c @@ -2895,7 +2895,7 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,

/* Allocate page for receive rings */ err = mlx4_alloc_hwq_res(mdev->dev, &priv->res, - MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE); + MLX4_EN_PAGE_SIZE); if (err) { en_err(priv, "Failed to allocate page for rx qps\n"); goto out; diff --git a/drivers/net/ethernet/mellanox/mlx4/en_resources.c b/drivers/net/ethernet/mellanox/mlx4/en_resources.c index e482fa1b..e675dba 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_resources.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_resources.c @@ -80,38 +80,6 @@ void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, } }

- -int mlx4_en_map_buffer(struct mlx4_buf *buf) -{ - struct page **pages; - int i; - - if (BITS_PER_LONG == 64 || buf->nbufs == 1) - return 0; - - pages = kmalloc(sizeof *pages * buf->nbufs, GFP_KERNEL); - if (!pages) - return -ENOMEM; - - for (i = 0; i < buf->nbufs; ++i) - pages[i] = virt_to_page(buf->page_list[i].buf); - - buf->direct.buf = vmap(pages, buf->nbufs, VM_MAP, PAGE_KERNEL); - kfree(pages); - if (!buf->direct.buf) - return -ENOMEM; - - return 0; -} - -void mlx4_en_unmap_buffer(struct mlx4_buf *buf) -{ - if (BITS_PER_LONG == 64 || buf->nbufs == 1) - return; - - vunmap(buf->direct.buf); -} - void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event) { return; diff --git a/drivers/net/ethernet/mellanox/mlx4/en_rx.c b/drivers/net/ethernet/mellanox/mlx4/en_rx.c index 9c145dd..e36f3c6 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_rx.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_rx.c @@ -391,17 +391,11 @@ int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,

/* Allocate HW buffers on provided NUMA node */ set_dev_node(&mdev->dev->persist->pdev->dev, node); - err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, - ring->buf_size, 2 * PAGE_SIZE); + err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); if (err) goto err_info;

- err = mlx4_en_map_buffer(&ring->wqres.buf); - if (err) { - en_err(priv, "Failed to map RX buffer\n"); - goto err_hwq; - } ring->buf = ring->wqres.buf.direct.buf;

ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; @@ -409,8 +403,6 @@ int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, *pring = ring; return 0;

-err_hwq: - mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); err_info: vfree(ring->rx_info); ring->rx_info = NULL; @@ -514,7 +506,6 @@ void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, struct mlx4_en_dev *mdev = priv->mdev; struct mlx4_en_rx_ring *ring = *pring;

- mlx4_en_unmap_buffer(&ring->wqres.buf); mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); vfree(ring->rx_info); ring->rx_info = NULL; diff --git a/drivers/net/ethernet/mellanox/mlx4/en_tx.c b/drivers/net/ethernet/mellanox/mlx4/en_tx.c index c10d98f..47dd7a0 100644 --- a/drivers/net/ethernet/mellanox/mlx4/en_tx.c +++ b/drivers/net/ethernet/mellanox/mlx4/en_tx.c @@ -93,20 +93,13 @@ int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,

/* Allocate HW buffers on provided NUMA node */ set_dev_node(&mdev->dev->persist->pdev->dev, node); - err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, - 2 * PAGE_SIZE); + err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); set_dev_node(&mdev->dev->persist->pdev->dev, mdev->dev->numa_node); if (err) { en_err(priv, "Failed allocating hwq resources\n"); goto err_bounce; }

- err = mlx4_en_map_buffer(&ring->wqres.buf); - if (err) { - en_err(priv, "Failed to map TX buffer\n"); - goto err_hwq_res; - } - ring->buf = ring->wqres.buf.direct.buf;

en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d buf_size:%d dma:%llx\n", @@ -117,7 +110,7 @@ int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, MLX4_RESERVE_ETH_BF_QP); if (err) { en_err(priv, "failed reserving qp for TX ring\n"); - goto err_map; + goto err_hwq_res; }

err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp, GFP_KERNEL); @@ -154,8 +147,6 @@ int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv,

err_reserve: mlx4_qp_release_range(mdev->dev, ring->qpn, 1); -err_map: - mlx4_en_unmap_buffer(&ring->wqres.buf); err_hwq_res: mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); err_bounce: @@ -182,7 +173,6 @@ void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, mlx4_qp_remove(mdev->dev, &ring->qp); mlx4_qp_free(mdev->dev, &ring->qp); mlx4_qp_release_range(priv->mdev->dev, ring->qpn, 1); - mlx4_en_unmap_buffer(&ring->wqres.buf); mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); kfree(ring->bounce_buf); ring->bounce_buf = NULL; diff --git a/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h b/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h index 666d166..d34e785 100644 --- a/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h +++ b/drivers/net/ethernet/mellanox/mlx4/mlx4_en.h @@ -795,8 +795,6 @@ void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride, int is_tx, int rss, int qpn, int cqn, int user_prio, struct mlx4_qp_context *context); void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event); -int mlx4_en_map_buffer(struct mlx4_buf *buf); -void mlx4_en_unmap_buffer(struct mlx4_buf *buf);

void mlx4_en_calc_rx_buf(struct net_device *dev); int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv); diff --git a/drivers/net/ethernet/mellanox/mlx4/mr.c b/drivers/net/ethernet/mellanox/mlx4/mr.c index 78f51e1..095f3ca 100644 --- a/drivers/net/ethernet/mellanox/mlx4/mr.c +++ b/drivers/net/ethernet/mellanox/mlx4/mr.c @@ -802,10 +802,7 @@ int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, return -ENOMEM;

for (i = 0; i < buf->npages; ++i) - if (buf->nbufs == 1) - page_list[i] = buf->direct.map + (i << buf->page_shift); - else - page_list[i] = buf->page_list[i].map; + page_list[i] = buf->direct.map + (i << buf->page_shift);

err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);

diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index fd13c1c..3d33739 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h @@ -595,7 +595,6 @@ struct mlx4_buf_list {

struct mlx4_buf { struct mlx4_buf_list direct; - struct mlx4_buf_list *page_list; int nbufs; int npages; int page_shift; @@ -1024,16 +1023,12 @@ static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; }

-int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, +int mlx4_buf_alloc(struct mlx4_dev *dev, int size, struct mlx4_buf *buf, gfp_t gfp); void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) { - if (BITS_PER_LONG == 64 || buf->nbufs == 1) - return buf->direct.buf + offset; - else - return buf->page_list[offset >> PAGE_SHIFT].buf + - (offset & (PAGE_SIZE - 1)); + return buf->direct.buf + offset; }

int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); @@ -1069,7 +1064,7 @@ int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);

int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, - int size, int max_direct); + int size); void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, int size);

From: Robert Richter rrichter@cavium.com

Some GIC revisions require an individual configuration to esp. add workarounds for HW bugs. This patch implements generic code to parse the hw revision provided by an IIDR register value and runs specific code if hw matches. There are functions that read the IIDR registers for GICV3 and ITS (GICD_IIDR/GITS_IIDR) and then go through a list of init functions to be called for specific versions.

The patch is needed to implement workarounds for HW errata in Cavium's ThunderX GICV3.

Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/irqchip/irq-gic-common.c | 11 +++++++++++ drivers/irqchip/irq-gic-common.h | 9 +++++++++ drivers/irqchip/irq-gic-v3-its.c | 15 +++++++++++++++ drivers/irqchip/irq-gic-v3.c | 14 ++++++++++++++ 4 files changed, 49 insertions(+)

diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c index 9448e39..a55a609 100644 --- a/drivers/irqchip/irq-gic-common.c +++ b/drivers/irqchip/irq-gic-common.c @@ -21,6 +21,17 @@

#include "irq-gic-common.h"

+void gic_check_capabilities(u32 iidr, const struct gic_capabilities *cap, + void *data) +{ + for (; cap->desc; cap++) { + if ((iidr & cap->mask) != cap->id) + continue; + cap->init(data); + pr_info("%s\n", cap->desc); + } +} + int gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)) { diff --git a/drivers/irqchip/irq-gic-common.h b/drivers/irqchip/irq-gic-common.h index 35a9884..90d55b9 100644 --- a/drivers/irqchip/irq-gic-common.h +++ b/drivers/irqchip/irq-gic-common.h @@ -20,10 +20,19 @@ #include <linux/of.h> #include <linux/irqdomain.h>

+struct gic_capabilities { + const char *desc; + void (*init)(void *data); + u32 id; + u32 mask; +}; + int gic_configure_irq(unsigned int irq, unsigned int type, void __iomem *base, void (*sync_access)(void)); void gic_dist_config(void __iomem *base, int gic_irqs, void (*sync_access)(void)); void gic_cpu_config(void __iomem *base, void (*sync_access)(void)); +void gic_check_capabilities(u32 iidr, const struct gic_capabilities *cap, + void *data);

#endif /* _IRQ_GIC_COMMON_H */ diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 3542c75..47a9595 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -36,6 +36,7 @@ #include <asm/cputype.h> #include <asm/exception.h>

+#include "irq-gic-common.h" #include "irqchip.h"

#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1 << 0) @@ -1432,6 +1433,18 @@ static int its_force_quiescent(void __iomem *base) } }

+static const struct gic_capabilities its_errata[] = { + { + } +}; + +static void its_check_capabilities(struct its_node *its) +{ + u32 iidr = readl_relaxed(its->base + GITS_IIDR); + + gic_check_capabilities(iidr, its_errata, its); +} + static int its_probe(struct device_node *node, struct irq_domain *parent) { struct resource res; @@ -1490,6 +1503,8 @@ static int its_probe(struct device_node *node, struct irq_domain *parent) } its->cmd_write = its->cmd_base;

+ its_check_capabilities(its); + err = its_alloc_tables(its); if (err) goto out_free_cmd; diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 0019fed..7857943 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -771,6 +771,18 @@ static const struct irq_domain_ops gic_irq_domain_ops = { .free = gic_irq_domain_free, };

+static const struct gic_capabilities gicv3_errata[] = { + { + } +}; + +static void gicv3_check_capabilities(void) +{ + u32 iidr = readl_relaxed(gic_data.dist_base + GICD_IIDR); + + gic_check_capabilities(iidr, gicv3_errata, NULL); +} + static int __init gic_of_init(struct device_node *node, struct device_node *parent) { void __iomem *dist_base; @@ -830,6 +842,8 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare gic_data.nr_redist_regions = nr_redist_regions; gic_data.redist_stride = redist_stride;

+ gicv3_check_capabilities(); + /* * Find out how many interrupts are supported. * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI)

From: Robert Richter rrichter@cavium.com

This implements two gicv3-its errata for ThunderX. Both with small impact affecting only ITS table allocation.

erratum 22375: only alloc 8MB table size erratum 24313: ignore memory access type

The fixes are in ITS initialization and basically ignore memory access type and table size provided by the TYPER and BASER registers.

Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/irqchip/irq-gic-v3-its.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 47a9595..d22bc39 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -39,7 +39,8 @@ #include "irq-gic-common.h" #include "irqchip.h"

-#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1 << 0) +#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING (1ULL << 0) +#define ITS_FLAGS_CAVIUM_THUNDERX (1ULL << 1)

#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING (1 << 0)

@@ -838,9 +839,22 @@ static int its_alloc_tables(struct its_node *its) int i; int psz = SZ_64K; u64 shr = GITS_BASER_InnerShareable; - u64 cache = GITS_BASER_WaWb; - u64 typer = readq_relaxed(its->base + GITS_TYPER); - u32 ids = GITS_TYPER_DEVBITS(typer); + u64 cache; + u64 typer; + u32 ids; + + if (its->flags & ITS_FLAGS_CAVIUM_THUNDERX) { + /* + * erratum 22375: only alloc 8MB table size + * erratum 24313: ignore memory access type + */ + cache = 0; + ids = 0x13; /* 20 bits, 8MB */ + } else { + cache = GITS_BASER_WaWb; + typer = readq_relaxed(its->base + GITS_TYPER); + ids = GITS_TYPER_DEVBITS(typer); + }

for (i = 0; i < GITS_BASER_NR_REGS; i++) { u64 val = readq_relaxed(its->base + GITS_BASER + i * 8); @@ -1433,8 +1447,21 @@ static int its_force_quiescent(void __iomem *base) } }

+static void its_enable_cavium_thunderx(void *data) +{ + struct its_node *its = data; + + its->flags |= ITS_FLAGS_CAVIUM_THUNDERX; +} + static const struct gic_capabilities its_errata[] = { { + .desc = "ITS: Cavium errata 22375, 24313", + .id = 0xa100034c, /* ThunderX pass 1.x */ + .mask = 0xffff0fff, + .init = its_enable_cavium_thunderx, + }, + { } };

From: Radha Mohan Chintakuntla rchintakuntla@cavium.com

In case of ARCH_THUNDER, there is a need to allocate the GICv3 ITS table which is bigger than the allowed max order. So we are forcing it only in case of 4KB page size.

Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/Kconfig | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 318175f..e32e427 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -595,6 +595,7 @@ config XEN config FORCE_MAX_ZONEORDER int default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE) + default "13" if (ARCH_THUNDER && !ARM64_64K_PAGES) default "11"

menuconfig ARMV8_DEPRECATED

From: Andre Przywara andre.przywara@arm.com

Currently we track which IRQ has been mapped to which VGIC list register and also have to synchronize both. We used to do this to hold some extra state (for instance the active bit). It turns out that this extra state in the LRs is no longer needed and this extra tracking causes some pain later. Remove the tracking feature (lr_map and lr_used) and get rid of quite some code on the way. On a guest exit we pick up all still pending IRQs from the LRs and put them back in the distributor. We don't care about active-only IRQs, so we keep them in the LRs. They will be retired either by our vgic_process_maintenance() routine or by the GIC hardware in case of edge triggered interrupts. In places where we scan LRs we now use our shadow copy of the ELRSR register directly. This code change means we lose the "piggy-back" optimization, which would re-use an active-only LR to inject the pending state on top of it. Tracing with various workloads shows that this actually occurred very rarely, the ballpark figure is about once every 10,000 exits in a disk I/O heavy workload. Also the list registers don't seem to as scarce as assumed, with all 4 LRs on the popular implementations used less than once every 100,000 exits.

This has been briefly tested on Midway, Juno and the model (the latter both with GICv2 and GICv3 guests).

Signed-off-by: Andre Przywara andre.przywara@arm.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- include/kvm/arm_vgic.h | 6 --- virt/kvm/arm/vgic-v2.c | 1 + virt/kvm/arm/vgic-v3.c | 1 + virt/kvm/arm/vgic.c | 143 ++++++++++++++++++++++--------------------------- 4 files changed, 66 insertions(+), 85 deletions(-)

diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 133ea00..2ccfa9a 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -279,9 +279,6 @@ struct vgic_v3_cpu_if { };

struct vgic_cpu { - /* per IRQ to LR mapping */ - u8 *vgic_irq_lr_map; - /* Pending/active/both interrupts on this VCPU */ DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS); DECLARE_BITMAP( active_percpu, VGIC_NR_PRIVATE_IRQS); @@ -292,9 +289,6 @@ struct vgic_cpu { unsigned long *active_shared; unsigned long *pend_act_shared;

- /* Bitmap of used/free list registers */ - DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS); - /* Number of list registers on this CPU */ int nr_lr;

diff --git a/virt/kvm/arm/vgic-v2.c b/virt/kvm/arm/vgic-v2.c index f9b9c7c..f723710 100644 --- a/virt/kvm/arm/vgic-v2.c +++ b/virt/kvm/arm/vgic-v2.c @@ -144,6 +144,7 @@ static void vgic_v2_enable(struct kvm_vcpu *vcpu) * anyway. */ vcpu->arch.vgic_cpu.vgic_v2.vgic_vmcr = 0; + vcpu->arch.vgic_cpu.vgic_v2.vgic_elrsr = ~0;

/* Get the show on the road... */ vcpu->arch.vgic_cpu.vgic_v2.vgic_hcr = GICH_HCR_EN; diff --git a/virt/kvm/arm/vgic-v3.c b/virt/kvm/arm/vgic-v3.c index dff0602..21e5d28 100644 --- a/virt/kvm/arm/vgic-v3.c +++ b/virt/kvm/arm/vgic-v3.c @@ -178,6 +178,7 @@ static void vgic_v3_enable(struct kvm_vcpu *vcpu) * anyway. */ vgic_v3->vgic_vmcr = 0; + vgic_v3->vgic_elrsr = ~0;

/* * If we are emulating a GICv3, we do it in an non-GICv2-compatible diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index bc40137..394622c 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -79,7 +79,6 @@ #include "vgic.h"

static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu); -static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu); static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr); static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc);

@@ -647,6 +646,17 @@ bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, return false; }

+static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, + struct vgic_lr vlr) +{ + vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); +} + +static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) +{ + return vgic_ops->get_elrsr(vcpu); +} + /** * vgic_unqueue_irqs - move pending/active IRQs from LRs to the distributor * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs @@ -658,9 +668,11 @@ bool vgic_handle_cfg_reg(u32 *reg, struct kvm_exit_mmio *mmio, void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) { struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + u64 elrsr = vgic_get_elrsr(vcpu); + unsigned long *elrsr_ptr = u64_to_bitmask(&elrsr); int i;

- for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) { + for_each_clear_bit(i, elrsr_ptr, vgic_cpu->nr_lr) { struct vgic_lr lr = vgic_get_lr(vcpu, i);

/* @@ -703,7 +715,7 @@ void vgic_unqueue_irqs(struct kvm_vcpu *vcpu) * Mark the LR as free for other use. */ BUG_ON(lr.state & LR_STATE_MASK); - vgic_retire_lr(i, lr.irq, vcpu); + vgic_sync_lr_elrsr(vcpu, i, lr); vgic_irq_clear_queued(vcpu, lr.irq);

/* Finally update the VGIC state. */ @@ -1011,17 +1023,6 @@ static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, vgic_ops->set_lr(vcpu, lr, vlr); }

-static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr, - struct vgic_lr vlr) -{ - vgic_ops->sync_lr_elrsr(vcpu, lr, vlr); -} - -static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu) -{ - return vgic_ops->get_elrsr(vcpu); -} - static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu) { return vgic_ops->get_eisr(vcpu); @@ -1062,18 +1063,6 @@ static inline void vgic_enable(struct kvm_vcpu *vcpu) vgic_ops->enable(vcpu); }

-static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) -{ - struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; - struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr); - - vlr.state = 0; - vgic_set_lr(vcpu, lr_nr, vlr); - clear_bit(lr_nr, vgic_cpu->lr_used); - vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY; - vgic_sync_lr_elrsr(vcpu, lr_nr, vlr); -} - /* * An interrupt may have been disabled after being made pending on the * CPU interface (the classic case is a timer running while we're @@ -1085,23 +1074,32 @@ static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu) */ static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) { - struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; + u64 elrsr = vgic_get_elrsr(vcpu); + unsigned long *elrsr_ptr = u64_to_bitmask(&elrsr); int lr; + struct vgic_lr vlr;

- for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) { - struct vgic_lr vlr = vgic_get_lr(vcpu, lr); + for_each_clear_bit(lr, elrsr_ptr, vgic->nr_lr) { + vlr = vgic_get_lr(vcpu, lr);

if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { - vgic_retire_lr(lr, vlr.irq, vcpu); - if (vgic_irq_is_queued(vcpu, vlr.irq)) - vgic_irq_clear_queued(vcpu, vlr.irq); + vlr.state = 0; + vgic_set_lr(vcpu, lr, vlr); + vgic_sync_lr_elrsr(vcpu, lr, vlr); + vgic_irq_clear_queued(vcpu, vlr.irq); } } }

static void vgic_queue_irq_to_lr(struct kvm_vcpu *vcpu, int irq, - int lr_nr, struct vgic_lr vlr) + int lr_nr, int sgi_source_id) { + struct vgic_lr vlr; + + vlr.state = 0; + vlr.irq = irq; + vlr.source = sgi_source_id; + if (vgic_irq_is_active(vcpu, irq)) { vlr.state |= LR_STATE_ACTIVE; kvm_debug("Set active, clear distributor: 0x%x\n", vlr.state); @@ -1126,9 +1124,9 @@ static void vgic_queue_irq_to_lr(struct kvm_vcpu *vcpu, int irq, */ bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) { - struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; struct vgic_dist *dist = &vcpu->kvm->arch.vgic; - struct vgic_lr vlr; + u64 elrsr = vgic_get_elrsr(vcpu); + unsigned long *elrsr_ptr = u64_to_bitmask(&elrsr); int lr;

/* Sanitize the input... */ @@ -1138,42 +1136,20 @@ bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)

kvm_debug("Queue IRQ%d\n", irq);

- lr = vgic_cpu->vgic_irq_lr_map[irq]; - - /* Do we have an active interrupt for the same CPUID? */ - if (lr != LR_EMPTY) { - vlr = vgic_get_lr(vcpu, lr); - if (vlr.source == sgi_source_id) { - kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq); - BUG_ON(!test_bit(lr, vgic_cpu->lr_used)); - vgic_queue_irq_to_lr(vcpu, irq, lr, vlr); - return true; - } - } + lr = find_first_bit(elrsr_ptr, vgic->nr_lr);

- /* Try to use another LR for this interrupt */ - lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used, - vgic->nr_lr); if (lr >= vgic->nr_lr) return false;

kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id); - vgic_cpu->vgic_irq_lr_map[irq] = lr; - set_bit(lr, vgic_cpu->lr_used);

- vlr.irq = irq; - vlr.source = sgi_source_id; - vlr.state = 0; - vgic_queue_irq_to_lr(vcpu, irq, lr, vlr); + vgic_queue_irq_to_lr(vcpu, irq, lr, sgi_source_id);

return true; }

static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq) { - if (!vgic_can_sample_irq(vcpu, irq)) - return true; /* level interrupt, already queued */ - if (vgic_queue_irq(vcpu, 0, irq)) { if (vgic_irq_is_edge(vcpu, irq)) { vgic_dist_irq_clear_pending(vcpu, irq); @@ -1346,29 +1322,44 @@ static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) struct vgic_dist *dist = &vcpu->kvm->arch.vgic; u64 elrsr; unsigned long *elrsr_ptr; - int lr, pending; - bool level_pending; + struct vgic_lr vlr; + int lr_nr; + bool pending; + + pending = vgic_process_maintenance(vcpu);

- level_pending = vgic_process_maintenance(vcpu); elrsr = vgic_get_elrsr(vcpu); elrsr_ptr = u64_to_bitmask(&elrsr);

- /* Clear mappings for empty LRs */ - for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) { - struct vgic_lr vlr; + for_each_clear_bit(lr_nr, elrsr_ptr, vgic_cpu->nr_lr) { + vlr = vgic_get_lr(vcpu, lr_nr); + + BUG_ON(!(vlr.state & LR_STATE_MASK)); + pending = true;

- if (!test_and_clear_bit(lr, vgic_cpu->lr_used)) + /* Reestablish SGI source for pending and active SGIs */ + if (vlr.irq < VGIC_NR_SGIS) + add_sgi_source(vcpu, vlr.irq, vlr.source); + + /* + * If the LR holds a pure active (10) interrupt then keep it + * in the LR without mirroring this status in the emulation. + */ + if (vlr.state == LR_STATE_ACTIVE) continue;

- vlr = vgic_get_lr(vcpu, lr); + if (vlr.state & LR_STATE_PENDING) + vgic_dist_irq_set_pending(vcpu, vlr.irq);

- BUG_ON(vlr.irq >= dist->nr_irqs); - vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY; + /* Mark this LR as empty now. */ + vlr.state = 0; + vgic_set_lr(vcpu, lr_nr, vlr); + vgic_sync_lr_elrsr(vcpu, lr_nr, vlr); } + vgic_update_state(vcpu->kvm);

- /* Check if we still have something up our sleeve... */ - pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr); - if (level_pending || pending < vgic->nr_lr) + /* vgic_update_state would not cover only-active IRQs */ + if (pending) set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); }

@@ -1590,11 +1581,9 @@ void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu) kfree(vgic_cpu->pending_shared); kfree(vgic_cpu->active_shared); kfree(vgic_cpu->pend_act_shared); - kfree(vgic_cpu->vgic_irq_lr_map); vgic_cpu->pending_shared = NULL; vgic_cpu->active_shared = NULL; vgic_cpu->pend_act_shared = NULL; - vgic_cpu->vgic_irq_lr_map = NULL; }

static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs) @@ -1605,18 +1594,14 @@ static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs) vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL); vgic_cpu->active_shared = kzalloc(sz, GFP_KERNEL); vgic_cpu->pend_act_shared = kzalloc(sz, GFP_KERNEL); - vgic_cpu->vgic_irq_lr_map = kmalloc(nr_irqs, GFP_KERNEL);

if (!vgic_cpu->pending_shared || !vgic_cpu->active_shared - || !vgic_cpu->pend_act_shared - || !vgic_cpu->vgic_irq_lr_map) { + || !vgic_cpu->pend_act_shared) { kvm_vgic_vcpu_destroy(vcpu); return -ENOMEM; }

- memset(vgic_cpu->vgic_irq_lr_map, LR_EMPTY, nr_irqs); - /* * Store the number of LRs per vcpu, so we don't have to go * all the way to the distributor structure to find out. Only

From: Andre Przywara andre.przywara@arm.com

Currently we destroy the VGIC emulation in one function that cares for all emulated models. To be on par with init_model (which is model specific), lets introduce a per-emulation-model destroy method, too. Use it for a tiny GICv3 specific code already, later it will be handy for the ITS emulation.

Signed-off-by: Andre Przywara andre.przywara@arm.com Reviewed-by: Eric Auger eric.auger@linaro.org Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- include/kvm/arm_vgic.h | 1 + virt/kvm/arm/vgic-v3-emul.c | 9 +++++++++ virt/kvm/arm/vgic.c | 11 ++++++++++- 3 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 2ccfa9a..b18e2c5 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -144,6 +144,7 @@ struct vgic_vm_ops { bool (*queue_sgi)(struct kvm_vcpu *, int irq); void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source); int (*init_model)(struct kvm *); + void (*destroy_model)(struct kvm *); int (*map_resources)(struct kvm *, const struct vgic_params *); };

diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c index e661e7f..d2eeb20 100644 --- a/virt/kvm/arm/vgic-v3-emul.c +++ b/virt/kvm/arm/vgic-v3-emul.c @@ -862,6 +862,14 @@ static int vgic_v3_init_model(struct kvm *kvm) return 0; }

+static void vgic_v3_destroy_model(struct kvm *kvm) +{ + struct vgic_dist *dist = &kvm->arch.vgic; + + kfree(dist->irq_spi_mpidr); + dist->irq_spi_mpidr = NULL; +} + /* GICv3 does not keep track of SGI sources anymore. */ static void vgic_v3_add_sgi_source(struct kvm_vcpu *vcpu, int irq, int source) { @@ -874,6 +882,7 @@ void vgic_v3_init_emulation(struct kvm *kvm) dist->vm_ops.queue_sgi = vgic_v3_queue_sgi; dist->vm_ops.add_sgi_source = vgic_v3_add_sgi_source; dist->vm_ops.init_model = vgic_v3_init_model; + dist->vm_ops.destroy_model = vgic_v3_destroy_model; dist->vm_ops.map_resources = vgic_v3_map_resources;

kvm->arch.max_vcpus = KVM_MAX_VCPUS; diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 394622c..cc8f5ed 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -100,6 +100,14 @@ int kvm_vgic_map_resources(struct kvm *kvm) return kvm->arch.vgic.vm_ops.map_resources(kvm, vgic); }

+static void vgic_destroy_model(struct kvm *kvm) +{ + struct vgic_vm_ops *vm_ops = &kvm->arch.vgic.vm_ops; + + if (vm_ops->destroy_model) + vm_ops->destroy_model(kvm); +} + /* * struct vgic_bitmap contains a bitmap made of unsigned longs, but * extracts u32s out of them. @@ -1629,6 +1637,8 @@ void kvm_vgic_destroy(struct kvm *kvm) struct kvm_vcpu *vcpu; int i;

+ vgic_destroy_model(kvm); + kvm_for_each_vcpu(i, vcpu, kvm) kvm_vgic_vcpu_destroy(vcpu);

@@ -1645,7 +1655,6 @@ void kvm_vgic_destroy(struct kvm *kvm) } kfree(dist->irq_sgi_sources); kfree(dist->irq_spi_cpu); - kfree(dist->irq_spi_mpidr); kfree(dist->irq_spi_target); kfree(dist->irq_pending_on_cpu); kfree(dist->irq_active_on_cpu);

From: Andre Przywara andre.przywara@arm.com

Currently we initialize all the possible GIC frame addresses in one function, without looking at the specific GIC model we instantiate for the guest. As this gets confusing when adding another VGIC model later, lets move these initializations into the respective model's init functions.

Signed-off-by: Andre Przywara andre.przywara@arm.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- virt/kvm/arm/vgic-v2-emul.c | 3 +++ virt/kvm/arm/vgic-v3-emul.c | 3 +++ virt/kvm/arm/vgic.c | 3 --- 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/virt/kvm/arm/vgic-v2-emul.c b/virt/kvm/arm/vgic-v2-emul.c index 1390797..8faa28c 100644 --- a/virt/kvm/arm/vgic-v2-emul.c +++ b/virt/kvm/arm/vgic-v2-emul.c @@ -567,6 +567,9 @@ void vgic_v2_init_emulation(struct kvm *kvm) dist->vm_ops.init_model = vgic_v2_init_model; dist->vm_ops.map_resources = vgic_v2_map_resources;

+ dist->vgic_cpu_base = VGIC_ADDR_UNDEF; + dist->vgic_dist_base = VGIC_ADDR_UNDEF; + kvm->arch.max_vcpus = VGIC_V2_MAX_CPUS; }

diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c index d2eeb20..1f42348 100644 --- a/virt/kvm/arm/vgic-v3-emul.c +++ b/virt/kvm/arm/vgic-v3-emul.c @@ -885,6 +885,9 @@ void vgic_v3_init_emulation(struct kvm *kvm) dist->vm_ops.destroy_model = vgic_v3_destroy_model; dist->vm_ops.map_resources = vgic_v3_map_resources;

+ dist->vgic_dist_base = VGIC_ADDR_UNDEF; + dist->vgic_redist_base = VGIC_ADDR_UNDEF; + kvm->arch.max_vcpus = KVM_MAX_VCPUS; }

diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index cc8f5ed..59f1801 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -1830,9 +1830,6 @@ int kvm_vgic_create(struct kvm *kvm, u32 type) kvm->arch.vgic.in_kernel = true; kvm->arch.vgic.vgic_model = type; kvm->arch.vgic.vctrl_base = vgic->vctrl_base; - kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF; - kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF; - kvm->arch.vgic.vgic_redist_base = VGIC_ADDR_UNDEF;

out_unlock: for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {

From: Andre Przywara andre.przywara@arm.com

In the GICv3 redistributor there are the PENDBASER and PROPBASER registers which we did not emulate so far, as they only make sense when having an ITS. In preparation for that emulate those MMIO accesses by storing the 64-bit data written into it into a variable which we later read in the ITS emulation.

Signed-off-by: Andre Przywara andre.przywara@arm.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- include/kvm/arm_vgic.h | 8 ++++++++ virt/kvm/arm/vgic-v3-emul.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ virt/kvm/arm/vgic.c | 35 +++++++++++++++++++++++++++++++++++ virt/kvm/arm/vgic.h | 4 ++++ 4 files changed, 91 insertions(+)

diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 3ee063b..8c6cb0e 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -256,6 +256,14 @@ struct vgic_dist { struct vgic_vm_ops vm_ops; struct vgic_io_device dist_iodev; struct vgic_io_device *redist_iodevs; + + /* Address of LPI configuration table shared by all redistributors */ + u64 propbaser; + + /* Addresses of LPI pending tables per redistributor */ + u64 *pendbaser; + + bool lpis_enabled; };

struct vgic_v2_cpu_if { diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c index a8cf669..5269ad1 100644 --- a/virt/kvm/arm/vgic-v3-emul.c +++ b/virt/kvm/arm/vgic-v3-emul.c @@ -651,6 +651,38 @@ static bool handle_mmio_cfg_reg_redist(struct kvm_vcpu *vcpu, return vgic_handle_cfg_reg(reg, mmio, offset); }

+/* We don't trigger any actions here, just store the register value */ +static bool handle_mmio_propbaser_redist(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + int mode = ACCESS_READ_VALUE; + + /* Storing a value with LPIs already enabled is undefined */ + mode |= dist->lpis_enabled ? ACCESS_WRITE_IGNORED : ACCESS_WRITE_VALUE; + vgic_handle_base_register(vcpu, mmio, offset, &dist->propbaser, mode); + + return false; +} + +/* We don't trigger any actions here, just store the register value */ +static bool handle_mmio_pendbaser_redist(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset) +{ + struct kvm_vcpu *rdvcpu = mmio->private; + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; + int mode = ACCESS_READ_VALUE; + + /* Storing a value with LPIs already enabled is undefined */ + mode |= dist->lpis_enabled ? ACCESS_WRITE_IGNORED : ACCESS_WRITE_VALUE; + vgic_handle_base_register(vcpu, mmio, offset, + &dist->pendbaser[rdvcpu->vcpu_id], mode); + + return false; +} + #define SGI_base(x) ((x) + SZ_64K)

static const struct vgic_io_range vgic_redist_ranges[] = { @@ -679,6 +711,18 @@ static const struct vgic_io_range vgic_redist_ranges[] = { .handle_mmio = handle_mmio_raz_wi, }, { + .base = GICR_PENDBASER, + .len = 0x08, + .bits_per_irq = 0, + .handle_mmio = handle_mmio_pendbaser_redist, + }, + { + .base = GICR_PROPBASER, + .len = 0x08, + .bits_per_irq = 0, + .handle_mmio = handle_mmio_propbaser_redist, + }, + { .base = GICR_IDREGS, .len = 0x30, .bits_per_irq = 0, diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 15e447f..49ee92b 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -446,6 +446,41 @@ void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, } }

+/* handle a 64-bit register access */ +void vgic_handle_base_register(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset, u64 *basereg, + int mode) +{ + u32 reg; + u64 breg; + + switch (offset & ~3) { + case 0x00: + breg = *basereg; + reg = lower_32_bits(breg); + vgic_reg_access(mmio, &reg, offset & 3, mode); + if (mmio->is_write && (mode & ACCESS_WRITE_VALUE)) { + breg &= GENMASK_ULL(63, 32); + breg |= reg; + *basereg = breg; + } + break; + case 0x04: + breg = *basereg; + reg = upper_32_bits(breg); + vgic_reg_access(mmio, &reg, offset & 3, mode); + if (mmio->is_write && (mode & ACCESS_WRITE_VALUE)) { + breg = lower_32_bits(breg); + breg |= (u64)reg << 32; + *basereg = breg; + } + break; + } +} + + + bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) { diff --git a/virt/kvm/arm/vgic.h b/virt/kvm/arm/vgic.h index a093f5c..b2d791c 100644 --- a/virt/kvm/arm/vgic.h +++ b/virt/kvm/arm/vgic.h @@ -71,6 +71,10 @@ void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg, phys_addr_t offset, int mode); bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset); +void vgic_handle_base_register(struct kvm_vcpu *vcpu, + struct kvm_exit_mmio *mmio, + phys_addr_t offset, u64 *basereg, + int mode);

static inline u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)

From: Andre Przywara andre.przywara@arm.com

Add emulation for some basic MMIO registers used in the ITS emulation. This includes: - GITS_{CTLR,TYPER,IIDR} - ID registers - GITS_{CBASER,CREADR,CWRITER} those implement the ITS command buffer handling

Most of the handlers are pretty straight forward, but CWRITER goes some extra miles to allow fine grained locking. The idea here is to let only the first instance iterate through the command ring buffer, CWRITER accesses on other VCPUs meanwhile will be picked up by that first instance and handled as well. The ITS lock is thus only hold for very small periods of time and is dropped before the actual command handler is called.

Signed-off-by: Andre Przywara andre.przywara@arm.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- include/kvm/arm_vgic.h | 3 + include/linux/irqchip/arm-gic-v3.h | 8 ++ virt/kvm/arm/its-emul.c | 205 +++++++++++++++++++++++++++++++++++++ virt/kvm/arm/its-emul.h | 1 + virt/kvm/arm/vgic-v3-emul.c | 2 + 5 files changed, 219 insertions(+)

diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 9e9d4aa..b432055 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -159,6 +159,9 @@ struct vgic_io_device { struct vgic_its { bool enabled; spinlock_t lock; + u64 cbaser; + int creadr; + int cwriter; };

struct vgic_dist { diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 24d156d..9d173d7 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -179,15 +179,23 @@ #define GITS_BASER 0x0100 #define GITS_IDREGS_BASE 0xffd0 #define GITS_PIDR2 GICR_PIDR2 +#define GITS_PIDR4 0xffd0 +#define GITS_CIDR0 0xfff0 +#define GITS_CIDR1 0xfff4 +#define GITS_CIDR2 0xfff8 +#define GITS_CIDR3 0xfffc

#define GITS_TRANSLATER 0x10040

#define GITS_CTLR_ENABLE (1U << 0) #define GITS_CTLR_QUIESCENT (1U << 31)

+#define GITS_TYPER_PLPIS (1UL << 0) +#define GITS_TYPER_IDBITS_SHIFT 8 #define GITS_TYPER_DEVBITS_SHIFT 13 #define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1) #define GITS_TYPER_PTA (1UL << 19) +#define GITS_TYPER_HWCOLLCNT_SHIFT 24

#define GITS_CBASER_VALID (1UL << 63) #define GITS_CBASER_nCnB (0UL << 59) diff --git a/virt/kvm/arm/its-emul.c b/virt/kvm/arm/its-emul.c index 659dd39..b498f06 100644 --- a/virt/kvm/arm/its-emul.c +++ b/virt/kvm/arm/its-emul.c @@ -32,10 +32,62 @@ #include "vgic.h" #include "its-emul.h"

+#define BASER_BASE_ADDRESS(x) ((x) & 0xfffffffff000ULL) + +/* The distributor lock is held by the VGIC MMIO handler. */ static bool handle_mmio_misc_gits(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) { + struct vgic_its *its = &vcpu->kvm->arch.vgic.its; + u32 reg; + bool was_enabled; + + switch (offset & ~3) { + case 0x00: /* GITS_CTLR */ + /* We never defer any command execution. */ + reg = GITS_CTLR_QUIESCENT; + if (its->enabled) + reg |= GITS_CTLR_ENABLE; + was_enabled = its->enabled; + vgic_reg_access(mmio, &reg, offset & 3, + ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); + its->enabled = !!(reg & GITS_CTLR_ENABLE); + return !was_enabled && its->enabled; + case 0x04: /* GITS_IIDR */ + reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0); + vgic_reg_access(mmio, &reg, offset & 3, + ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); + break; + case 0x08: /* GITS_TYPER */ + /* + * We use linear CPU numbers for redistributor addressing, + * so GITS_TYPER.PTA is 0. + * To avoid memory waste on the guest side, we keep the + * number of IDBits and DevBits low for the time being. + * This could later be made configurable by userland. + * Since we have all collections in linked list, we claim + * that we can hold all of the collection tables in our + * own memory and that the ITT entry size is 1 byte (the + * smallest possible one). + */ + reg = GITS_TYPER_PLPIS; + reg |= 0xff << GITS_TYPER_HWCOLLCNT_SHIFT; + reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT; + reg |= 0x0f << GITS_TYPER_IDBITS_SHIFT; + vgic_reg_access(mmio, &reg, offset & 3, + ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); + break; + case 0x0c: + /* The upper 32bits of TYPER are all 0 for the time being. + * Should we need more than 256 collections, we can enable + * some bits in here. + */ + vgic_reg_access(mmio, NULL, offset & 3, + ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); + break; + } + return false; }

@@ -43,20 +95,142 @@ static bool handle_mmio_gits_idregs(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) { + u32 reg = 0; + int idreg = (offset & ~3) + GITS_IDREGS_BASE; + + switch (idreg) { + case GITS_PIDR2: + reg = GIC_PIDR2_ARCH_GICv3; + break; + case GITS_PIDR4: + /* This is a 64K software visible page */ + reg = 0x40; + break; + /* Those are the ID registers for (any) GIC. */ + case GITS_CIDR0: + reg = 0x0d; + break; + case GITS_CIDR1: + reg = 0xf0; + break; + case GITS_CIDR2: + reg = 0x05; + break; + case GITS_CIDR3: + reg = 0xb1; + break; + } + vgic_reg_access(mmio, &reg, offset & 3, + ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); return false; }

+static int vits_handle_command(struct kvm_vcpu *vcpu, u64 *its_cmd) +{ + return -ENODEV; +} + static bool handle_mmio_gits_cbaser(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) { + struct vgic_its *its = &vcpu->kvm->arch.vgic.its; + int mode = ACCESS_READ_VALUE; + + mode |= its->enabled ? ACCESS_WRITE_IGNORED : ACCESS_WRITE_VALUE; + + vgic_handle_base_register(vcpu, mmio, offset, &its->cbaser, mode); + + /* Writing CBASER resets the read pointer. */ + if (mmio->is_write) + its->creadr = 0; + return false; }

+static int its_cmd_buffer_size(struct kvm *kvm) +{ + struct vgic_its *its = &kvm->arch.vgic.its; + + return ((its->cbaser & 0xff) + 1) << 12; +} + +static gpa_t its_cmd_buffer_base(struct kvm *kvm) +{ + struct vgic_its *its = &kvm->arch.vgic.its; + + return BASER_BASE_ADDRESS(its->cbaser); +} + +/* + * By writing to CWRITER the guest announces new commands to be processed. + * Since we cannot read from guest memory inside the ITS spinlock, we + * iterate over the command buffer (with the lock dropped) until the read + * pointer matches the write pointer. Other VCPUs writing this register in the + * meantime will just update the write pointer, leaving the command + * processing to the first instance of the function. + */ static bool handle_mmio_gits_cwriter(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) { + struct vgic_its *its = &vcpu->kvm->arch.vgic.its; + gpa_t cbaser = its_cmd_buffer_base(vcpu->kvm); + u64 cmd_buf[4]; + u32 reg; + bool finished; + + /* The upper 32 bits are RES0 */ + if ((offset & ~3) == 0x04) { + vgic_reg_access(mmio, &reg, offset & 3, + ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); + return false; + } + + reg = its->cwriter & 0xfffe0; + vgic_reg_access(mmio, &reg, offset & 3, + ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); + if (!mmio->is_write) + return false; + + reg &= 0xfffe0; + if (reg > its_cmd_buffer_size(vcpu->kvm)) + return false; + + spin_lock(&its->lock); + + /* + * If there is still another VCPU handling commands, let this + * one pick up the new CWRITER and process our new commands as well. + */ + finished = (its->cwriter != its->creadr); + its->cwriter = reg; + + spin_unlock(&its->lock); + + while (!finished) { + int ret = kvm_read_guest(vcpu->kvm, cbaser + its->creadr, + cmd_buf, 32); + if (ret) { + /* + * Gah, we are screwed. Reset CWRITER to that command + * that we have finished processing and return. + */ + spin_lock(&its->lock); + its->cwriter = its->creadr; + spin_unlock(&its->lock); + break; + } + vits_handle_command(vcpu, cmd_buf); + + spin_lock(&its->lock); + its->creadr += 32; + if (its->creadr == its_cmd_buffer_size(vcpu->kvm)) + its->creadr = 0; + finished = (its->creadr == its->cwriter); + spin_unlock(&its->lock); + } + return false; }

@@ -64,6 +238,20 @@ static bool handle_mmio_gits_creadr(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) { + struct vgic_its *its = &vcpu->kvm->arch.vgic.its; + u32 reg; + + switch (offset & ~3) { + case 0x00: + reg = its->creadr & 0xfffe0; + vgic_reg_access(mmio, &reg, offset & 3, + ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); + break; + case 0x04: + vgic_reg_access(mmio, &reg, offset & 3, + ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED); + break; + } return false; }

@@ -117,9 +305,26 @@ int vits_init(struct kvm *kvm) struct vgic_dist *dist = &kvm->arch.vgic; struct vgic_its *its = &dist->its;

+ dist->pendbaser = kmalloc(sizeof(u64) * dist->nr_cpus, GFP_KERNEL); + if (!dist->pendbaser) + return -ENOMEM; + spin_lock_init(&its->lock);

its->enabled = false;

return -ENXIO; } + +void vits_destroy(struct kvm *kvm) +{ + struct vgic_dist *dist = &kvm->arch.vgic; + struct vgic_its *its = &dist->its; + + if (!vgic_has_its(kvm)) + return; + + kfree(dist->pendbaser); + + its->enabled = false; +} diff --git a/virt/kvm/arm/its-emul.h b/virt/kvm/arm/its-emul.h index 5dc8e2f..472a6d0 100644 --- a/virt/kvm/arm/its-emul.h +++ b/virt/kvm/arm/its-emul.h @@ -31,5 +31,6 @@

void vgic_enable_lpis(struct kvm_vcpu *vcpu); int vits_init(struct kvm *kvm); +void vits_destroy(struct kvm *kvm);

#endif diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c index f5865e7..49be3c3 100644 --- a/virt/kvm/arm/vgic-v3-emul.c +++ b/virt/kvm/arm/vgic-v3-emul.c @@ -928,6 +928,8 @@ static void vgic_v3_destroy_model(struct kvm *kvm) { struct vgic_dist *dist = &kvm->arch.vgic;

+ vits_destroy(kvm); + kfree(dist->irq_spi_mpidr); dist->irq_spi_mpidr = NULL; }

From: Andre Przywara andre.przywara@arm.com

As the actual LPI number in a guest can be quite high, but is mostly assigned using a very sparse allocation scheme, bitmaps and arrays for storing the virtual interrupt status are a waste of memory. We use our equivalent of the "Interrupt Translation Table Entry" (ITTE) to hold this extra status information for a virtual LPI. As the normal VGIC code cannot use it's fancy bitmaps to manage pending interrupts, we provide a hook in the VGIC code to let the ITS emulation handle the list register queueing itself. LPIs are located in a separate number range (>=8192), so distinguishing them is easy. With LPIs being only edge-triggered, we get away with a less complex IRQ handling.

Signed-off-by: Andre Przywara andre.przywara@arm.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- include/kvm/arm_vgic.h | 2 ++ virt/kvm/arm/its-emul.c | 71 ++++++++++++++++++++++++++++++++++++++++++++ virt/kvm/arm/its-emul.h | 3 ++ virt/kvm/arm/vgic-v3-emul.c | 2 ++ virt/kvm/arm/vgic.c | 72 ++++++++++++++++++++++++++++++++++----------- 5 files changed, 133 insertions(+), 17 deletions(-)

diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 1648668..2a67a10 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -147,6 +147,8 @@ struct vgic_vm_ops { int (*init_model)(struct kvm *); void (*destroy_model)(struct kvm *); int (*map_resources)(struct kvm *, const struct vgic_params *); + bool (*queue_lpis)(struct kvm_vcpu *); + void (*unqueue_lpi)(struct kvm_vcpu *, int irq); };

struct vgic_io_device { diff --git a/virt/kvm/arm/its-emul.c b/virt/kvm/arm/its-emul.c index 7f217fa..b9c40d7 100644 --- a/virt/kvm/arm/its-emul.c +++ b/virt/kvm/arm/its-emul.c @@ -50,8 +50,26 @@ struct its_itte { struct its_collection *collection; u32 lpi; u32 event_id; + bool enabled; + unsigned long *pending; };

+#define for_each_lpi(dev, itte, kvm) \ + list_for_each_entry(dev, &(kvm)->arch.vgic.its.device_list, dev_list) \ + list_for_each_entry(itte, &(dev)->itt, itte_list) + +static struct its_itte *find_itte_by_lpi(struct kvm *kvm, int lpi) +{ + struct its_device *device; + struct its_itte *itte; + + for_each_lpi(device, itte, kvm) { + if (itte->lpi == lpi) + return itte; + } + return NULL; +} + #define BASER_BASE_ADDRESS(x) ((x) & 0xfffffffff000ULL)

/* The distributor lock is held by the VGIC MMIO handler. */ @@ -145,6 +163,59 @@ static bool handle_mmio_gits_idregs(struct kvm_vcpu *vcpu, return false; }

+/* + * Find all enabled and pending LPIs and queue them into the list + * registers. + * The dist lock is held by the caller. + */ +bool vits_queue_lpis(struct kvm_vcpu *vcpu) +{ + struct vgic_its *its = &vcpu->kvm->arch.vgic.its; + struct its_device *device; + struct its_itte *itte; + bool ret = true; + + if (!vgic_has_its(vcpu->kvm)) + return true; + if (!its->enabled || !vcpu->kvm->arch.vgic.lpis_enabled) + return true; + + spin_lock(&its->lock); + for_each_lpi(device, itte, vcpu->kvm) { + if (!itte->enabled || !test_bit(vcpu->vcpu_id, itte->pending)) + continue; + + if (!itte->collection) + continue; + + if (itte->collection->target_addr != vcpu->vcpu_id) + continue; + + __clear_bit(vcpu->vcpu_id, itte->pending); + + ret &= vgic_queue_irq(vcpu, 0, itte->lpi); + } + + spin_unlock(&its->lock); + return ret; +} + +/* Called with the distributor lock held by the caller. */ +void vits_unqueue_lpi(struct kvm_vcpu *vcpu, int lpi) +{ + struct vgic_its *its = &vcpu->kvm->arch.vgic.its; + struct its_itte *itte; + + spin_lock(&its->lock); + + /* Find the right ITTE and put the pending state back in there */ + itte = find_itte_by_lpi(vcpu->kvm, lpi); + if (itte) + __set_bit(vcpu->vcpu_id, itte->pending); + + spin_unlock(&its->lock); +} + static int vits_handle_command(struct kvm_vcpu *vcpu, u64 *its_cmd) { return -ENODEV; diff --git a/virt/kvm/arm/its-emul.h b/virt/kvm/arm/its-emul.h index 472a6d0..cc5d5ff 100644 --- a/virt/kvm/arm/its-emul.h +++ b/virt/kvm/arm/its-emul.h @@ -33,4 +33,7 @@ void vgic_enable_lpis(struct kvm_vcpu *vcpu); int vits_init(struct kvm *kvm); void vits_destroy(struct kvm *kvm);

+bool vits_queue_lpis(struct kvm_vcpu *vcpu); +void vits_unqueue_lpi(struct kvm_vcpu *vcpu, int irq); + #endif diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c index 49be3c3..4132c26 100644 --- a/virt/kvm/arm/vgic-v3-emul.c +++ b/virt/kvm/arm/vgic-v3-emul.c @@ -948,6 +948,8 @@ void vgic_v3_init_emulation(struct kvm *kvm) dist->vm_ops.init_model = vgic_v3_init_model; dist->vm_ops.destroy_model = vgic_v3_destroy_model; dist->vm_ops.map_resources = vgic_v3_map_resources; + dist->vm_ops.queue_lpis = vits_queue_lpis; + dist->vm_ops.unqueue_lpi = vits_unqueue_lpi;

dist->vgic_dist_base = VGIC_ADDR_UNDEF; dist->vgic_redist_base = VGIC_ADDR_UNDEF; diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 49ee92b..9dfd094 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -95,6 +95,20 @@ static bool queue_sgi(struct kvm_vcpu *vcpu, int irq) return vcpu->kvm->arch.vgic.vm_ops.queue_sgi(vcpu, irq); }

+static bool vgic_queue_lpis(struct kvm_vcpu *vcpu) +{ + if (vcpu->kvm->arch.vgic.vm_ops.queue_lpis) + return vcpu->kvm->arch.vgic.vm_ops.queue_lpis(vcpu); + else + return true; +} + +static void vgic_unqueue_lpi(struct kvm_vcpu *vcpu, int irq) +{ + if (vcpu->kvm->arch.vgic.vm_ops.unqueue_lpi) + vcpu->kvm->arch.vgic.vm_ops.unqueue_lpi(vcpu, irq); +} + int kvm_vgic_map_resources(struct kvm *kvm) { return kvm->arch.vgic.vm_ops.map_resources(kvm, vgic); @@ -1135,6 +1149,10 @@ static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) for_each_clear_bit(lr, elrsr_ptr, vgic->nr_lr) { vlr = vgic_get_lr(vcpu, lr);

+ /* We don't care about LPIs here */ + if (vlr.irq >= 8192) + continue; + if (!vgic_irq_is_enabled(vcpu, vlr.irq)) { vlr.state = 0; vgic_set_lr(vcpu, lr, vlr); @@ -1147,25 +1165,33 @@ static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu) static void vgic_queue_irq_to_lr(struct kvm_vcpu *vcpu, int irq, int lr_nr, int sgi_source_id) { + struct vgic_dist *dist = &vcpu->kvm->arch.vgic; struct vgic_lr vlr;

vlr.state = 0; vlr.irq = irq; vlr.source = sgi_source_id;

- if (vgic_irq_is_active(vcpu, irq)) { - vlr.state |= LR_STATE_ACTIVE; - kvm_debug("Set active, clear distributor: 0x%x\n", vlr.state); - vgic_irq_clear_active(vcpu, irq); - vgic_update_state(vcpu->kvm); - } else if (vgic_dist_irq_is_pending(vcpu, irq)) { - vlr.state |= LR_STATE_PENDING; - kvm_debug("Set pending: 0x%x\n", vlr.state); - } - - if (!vgic_irq_is_edge(vcpu, irq)) - vlr.state |= LR_EOI_INT; + /* We care only about state for SGIs/PPIs/SPIs, not for LPIs */ + if (irq < dist->nr_irqs) { + if (vgic_irq_is_active(vcpu, irq)) { + vlr.state |= LR_STATE_ACTIVE; + kvm_debug("Set active, clear distributor: 0x%x\n", + vlr.state); + vgic_irq_clear_active(vcpu, irq); + vgic_update_state(vcpu->kvm); + } else if (vgic_dist_irq_is_pending(vcpu, irq)) { + vlr.state |= LR_STATE_PENDING; + kvm_debug("Set pending: 0x%x\n", vlr.state); + }

+ if (!vgic_irq_is_edge(vcpu, irq)) + vlr.state |= LR_EOI_INT; + } else { + /* If this is an LPI, it can only be pending */ + if (irq >= 8192) + vlr.state |= LR_STATE_PENDING; + } vgic_set_lr(vcpu, lr_nr, vlr); vgic_sync_lr_elrsr(vcpu, lr_nr, vlr); } @@ -1177,7 +1203,6 @@ static void vgic_queue_irq_to_lr(struct kvm_vcpu *vcpu, int irq, */ bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) { - struct vgic_dist *dist = &vcpu->kvm->arch.vgic; u64 elrsr = vgic_get_elrsr(vcpu); unsigned long *elrsr_ptr = u64_to_bitmask(&elrsr); int lr; @@ -1185,7 +1210,6 @@ bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq) /* Sanitize the input... */ BUG_ON(sgi_source_id & ~7); BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS); - BUG_ON(irq >= dist->nr_irqs);

kvm_debug("Queue IRQ%d\n", irq);

@@ -1265,8 +1289,12 @@ static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) overflow = 1; }

- - + /* + * LPIs are not mapped in our bitmaps, so we leave the iteration + * to the ITS emulation code. + */ + if (!vgic_queue_lpis(vcpu)) + overflow = 1;

epilog: if (overflow) { @@ -1387,6 +1415,16 @@ static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) for_each_clear_bit(lr_nr, elrsr_ptr, vgic_cpu->nr_lr) { vlr = vgic_get_lr(vcpu, lr_nr);

+ /* LPIs are handled separately */ + if (vlr.irq >= 8192) { + /* We just need to take care about still pending LPIs */ + if (vlr.state & LR_STATE_PENDING) { + vgic_unqueue_lpi(vcpu, vlr.irq); + pending = true; + } + continue; + } + BUG_ON(!(vlr.state & LR_STATE_MASK)); pending = true;

@@ -1411,7 +1449,7 @@ static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) } vgic_update_state(vcpu->kvm);

- /* vgic_update_state would not cover only-active IRQs */ + /* vgic_update_state would not cover only-active IRQs or LPIs */ if (pending) set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu); }

From: Andre Przywara andre.przywara@arm.com

The connection between a device, an event ID, the LPI number and the allocated CPU is stored in in-memory tables in a GICv3, but their format is not specified by the spec. Instead software uses a command queue in a ring buffer to let the ITS implementation use their own format. Implement handlers for the various ITS commands and let them store the requested relation into our own data structures. To avoid kmallocs inside the ITS spinlock, we preallocate possibly needed memory outside of the lock and free that if it turns out to be not needed (mostly error handling). Error handling is very basic at this point, as we don't have a good way of communicating errors to the guest (usually a SError). The INT command handler is missing at this point, as we gain the capability of actually injecting MSIs into the guest only later on.

Signed-off-by: Andre Przywara andre.przywara@arm.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- include/linux/irqchip/arm-gic-v3.h | 5 +- virt/kvm/arm/its-emul.c | 497 ++++++++++++++++++++++++++++++++++++- virt/kvm/arm/its-emul.h | 11 + 3 files changed, 511 insertions(+), 2 deletions(-)

diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index 9d173d7..5bbd47c 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -254,7 +254,10 @@ */ #define GITS_CMD_MAPD 0x08 #define GITS_CMD_MAPC 0x09 -#define GITS_CMD_MAPVI 0x0a +#define GITS_CMD_MAPTI 0x0a +/* older GIC documentation used MAPVI for this command */ +#define GITS_CMD_MAPVI GITS_CMD_MAPTI +#define GITS_CMD_MAPI 0x0b #define GITS_CMD_MOVI 0x01 #define GITS_CMD_DISCARD 0x0f #define GITS_CMD_INV 0x0c diff --git a/virt/kvm/arm/its-emul.c b/virt/kvm/arm/its-emul.c index 05245cb..89534c6 100644 --- a/virt/kvm/arm/its-emul.c +++ b/virt/kvm/arm/its-emul.c @@ -22,6 +22,7 @@ #include <linux/kvm_host.h> #include <linux/interrupt.h> #include <linux/list.h> +#include <linux/slab.h>

#include <linux/irqchip/arm-gic-v3.h> #include <kvm/arm_vgic.h> @@ -55,6 +56,34 @@ struct its_itte { unsigned long *pending; };

+static struct its_device *find_its_device(struct kvm *kvm, u32 device_id) +{ + struct vgic_its *its = &kvm->arch.vgic.its; + struct its_device *device; + + list_for_each_entry(device, &its->device_list, dev_list) + if (device_id == device->device_id) + return device; + + return NULL; +} + +static struct its_itte *find_itte(struct kvm *kvm, u32 device_id, u32 event_id) +{ + struct its_device *device; + struct its_itte *itte; + + device = find_its_device(kvm, device_id); + if (device == NULL) + return NULL; + + list_for_each_entry(itte, &device->itt, itte_list) + if (itte->event_id == event_id) + return itte; + + return NULL; +} + #define for_each_lpi(dev, itte, kvm) \ list_for_each_entry(dev, &(kvm)->arch.vgic.its.device_list, dev_list) \ list_for_each_entry(itte, &(dev)->itt, itte_list) @@ -71,6 +100,19 @@ static struct its_itte *find_itte_by_lpi(struct kvm *kvm, int lpi) return NULL; }

+static struct its_collection *find_collection(struct kvm *kvm, int coll_id) +{ + struct its_collection *collection; + + list_for_each_entry(collection, &kvm->arch.vgic.its.collection_list, + coll_list) { + if (coll_id == collection->collection_id) + return collection; + } + + return NULL; +} + #define LPI_PROP_ENABLE_BIT(p) ((p) & LPI_PROP_ENABLED) #define LPI_PROP_PRIORITY(p) ((p) & 0xfc)

@@ -333,9 +375,461 @@ void vits_unqueue_lpi(struct kvm_vcpu *vcpu, int lpi) spin_unlock(&its->lock); }

+static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size) +{ + return (le64_to_cpu(its_cmd[word]) >> shift) & (BIT_ULL(size) - 1); +} + +#define its_cmd_get_command(cmd) its_cmd_mask_field(cmd, 0, 0, 8) +#define its_cmd_get_deviceid(cmd) its_cmd_mask_field(cmd, 0, 32, 32) +#define its_cmd_get_id(cmd) its_cmd_mask_field(cmd, 1, 0, 32) +#define its_cmd_get_physical_id(cmd) its_cmd_mask_field(cmd, 1, 32, 32) +#define its_cmd_get_collection(cmd) its_cmd_mask_field(cmd, 2, 0, 16) +#define its_cmd_get_target_addr(cmd) its_cmd_mask_field(cmd, 2, 16, 32) +#define its_cmd_get_validbit(cmd) its_cmd_mask_field(cmd, 2, 63, 1) + +/* The DISCARD command frees an Interrupt Translation Table Entry (ITTE). */ +static int vits_cmd_handle_discard(struct kvm *kvm, u64 *its_cmd) +{ + struct vgic_its *its = &kvm->arch.vgic.its; + u32 device_id; + u32 event_id; + struct its_itte *itte; + int ret = 0; + + device_id = its_cmd_get_deviceid(its_cmd); + event_id = its_cmd_get_id(its_cmd); + + spin_lock(&its->lock); + itte = find_itte(kvm, device_id, event_id); + if (!itte || !itte->collection) { + ret = E_ITS_DISCARD_UNMAPPED_INTERRUPT; + goto out_unlock; + } + + __clear_bit(itte->collection->target_addr, itte->pending); + + list_del(&itte->itte_list); + kfree(itte); +out_unlock: + spin_unlock(&its->lock); + return ret; +} + +/* The MOVI command moves an ITTE to a different collection. */ +static int vits_cmd_handle_movi(struct kvm *kvm, u64 *its_cmd) +{ + struct vgic_its *its = &kvm->arch.vgic.its; + u32 device_id = its_cmd_get_deviceid(its_cmd); + u32 event_id = its_cmd_get_id(its_cmd); + u32 coll_id = its_cmd_get_collection(its_cmd); + struct its_itte *itte; + struct its_collection *collection; + int ret; + + spin_lock(&its->lock); + itte = find_itte(kvm, device_id, event_id); + if (!itte) { + ret = E_ITS_MOVI_UNMAPPED_INTERRUPT; + goto out_unlock; + } + if (!itte->collection) { + ret = E_ITS_MOVI_UNMAPPED_COLLECTION; + goto out_unlock; + } + + collection = find_collection(kvm, coll_id); + if (!collection) { + ret = E_ITS_MOVI_UNMAPPED_COLLECTION; + goto out_unlock; + } + + if (test_and_clear_bit(itte->collection->target_addr, itte->pending)) + __set_bit(collection->target_addr, itte->pending); + + itte->collection = collection; +out_unlock: + spin_unlock(&its->lock); + return ret; +} + +static void vits_init_collection(struct kvm *kvm, + struct its_collection *collection, + u32 coll_id) +{ + collection->collection_id = coll_id; + + list_add_tail(&collection->coll_list, + &kvm->arch.vgic.its.collection_list); +} + +/* The MAPTI and MAPI commands map LPIs to ITTEs. */ +static int vits_cmd_handle_mapi(struct kvm *kvm, u64 *its_cmd, u8 cmd) +{ + struct vgic_dist *dist = &kvm->arch.vgic; + u32 device_id = its_cmd_get_deviceid(its_cmd); + u32 event_id = its_cmd_get_id(its_cmd); + u32 coll_id = its_cmd_get_collection(its_cmd); + struct its_itte *itte, *new_itte; + struct its_device *device; + struct its_collection *collection, *new_coll; + int lpi_nr; + int ret = 0; + + /* Preallocate possibly needed memory here outside of the lock */ + new_coll = kmalloc(sizeof(struct its_collection), GFP_KERNEL); + new_itte = kzalloc(sizeof(struct its_itte), GFP_KERNEL); + if (new_itte) + new_itte->pending = kcalloc(BITS_TO_LONGS(dist->nr_cpus), + sizeof(long), GFP_KERNEL); + + spin_lock(&dist->its.lock); + + device = find_its_device(kvm, device_id); + if (!device) { + ret = E_ITS_MAPTI_UNMAPPED_DEVICE; + goto out_unlock; + } + + collection = find_collection(kvm, coll_id); + if (!collection && !new_coll) { + ret = -ENOMEM; + goto out_unlock; + } + + if (cmd == GITS_CMD_MAPTI) + lpi_nr = its_cmd_get_physical_id(its_cmd); + else + lpi_nr = event_id; + if (lpi_nr < GIC_LPI_OFFSET || + lpi_nr >= nr_idbits_propbase(dist->propbaser)) { + ret = E_ITS_MAPTI_PHYSICALID_OOR; + goto out_unlock; + } + + itte = find_itte(kvm, device_id, event_id); + if (!itte) { + if (!new_itte || !new_itte->pending) { + ret = -ENOMEM; + goto out_unlock; + } + itte = new_itte; + + itte->event_id = event_id; + list_add_tail(&itte->itte_list, &device->itt); + } else { + if (new_itte) + kfree(new_itte->pending); + kfree(new_itte); + } + + if (!collection) { + collection = new_coll; + vits_init_collection(kvm, collection, coll_id); + } else { + kfree(new_coll); + } + + itte->collection = collection; + itte->lpi = lpi_nr; + +out_unlock: + spin_unlock(&dist->its.lock); + if (ret) { + kfree(new_coll); + if (new_itte) + kfree(new_itte->pending); + kfree(new_itte); + } + return ret; +} + +static void vits_unmap_device(struct kvm *kvm, struct its_device *device) +{ + struct its_itte *itte, *temp; + + /* + * The spec says that unmapping a device with still valid + * ITTEs associated is UNPREDICTABLE. We remove all ITTEs, + * since we cannot leave the memory unreferenced. + */ + list_for_each_entry_safe(itte, temp, &device->itt, itte_list) { + list_del(&itte->itte_list); + kfree(itte); + } + + list_del(&device->dev_list); + kfree(device); +} + +/* The MAPD command maps device IDs to Interrupt Translation Tables (ITTs). */ +static int vits_cmd_handle_mapd(struct kvm *kvm, u64 *its_cmd) +{ + struct vgic_its *its = &kvm->arch.vgic.its; + bool valid = its_cmd_get_validbit(its_cmd); + u32 device_id = its_cmd_get_deviceid(its_cmd); + struct its_device *device, *new_device = NULL; + + /* We preallocate memory outside of the lock here */ + if (valid) { + new_device = kzalloc(sizeof(struct its_device), GFP_KERNEL); + if (!new_device) + return -ENOMEM; + } + + spin_lock(&its->lock); + + device = find_its_device(kvm, device_id); + if (device) + vits_unmap_device(kvm, device); + + /* + * The spec does not say whether unmapping a not-mapped device + * is an error, so we are done in any case. + */ + if (!valid) + goto out_unlock; + + device = new_device; + + device->device_id = device_id; + INIT_LIST_HEAD(&device->itt); + + list_add_tail(&device->dev_list, + &kvm->arch.vgic.its.device_list); + +out_unlock: + spin_unlock(&its->lock); + return 0; +} + +/* The MAPC command maps collection IDs to redistributors. */ +static int vits_cmd_handle_mapc(struct kvm *kvm, u64 *its_cmd) +{ + struct vgic_its *its = &kvm->arch.vgic.its; + u16 coll_id; + u32 target_addr; + struct its_collection *collection, *new_coll = NULL; + bool valid; + + valid = its_cmd_get_validbit(its_cmd); + coll_id = its_cmd_get_collection(its_cmd); + target_addr = its_cmd_get_target_addr(its_cmd); + + if (target_addr >= atomic_read(&kvm->online_vcpus)) + return E_ITS_MAPC_PROCNUM_OOR; + + /* We preallocate memory outside of the lock here */ + if (valid) { + new_coll = kmalloc(sizeof(struct its_collection), GFP_KERNEL); + if (!new_coll) + return -ENOMEM; + } + + spin_lock(&its->lock); + collection = find_collection(kvm, coll_id); + + if (!valid) { + struct its_device *device; + struct its_itte *itte; + /* + * Clearing the mapping for that collection ID removes the + * entry from the list. If there wasn't any before, we can + * go home early. + */ + if (!collection) + goto out_unlock; + + for_each_lpi(device, itte, kvm) + if (itte->collection && + itte->collection->collection_id == coll_id) + itte->collection = NULL; + + list_del(&collection->coll_list); + kfree(collection); + } else { + if (!collection) + collection = new_coll; + else + kfree(new_coll); + + vits_init_collection(kvm, collection, coll_id); + collection->target_addr = target_addr; + } + +out_unlock: + spin_unlock(&its->lock); + return 0; +} + +/* The CLEAR command removes the pending state for a particular LPI. */ +static int vits_cmd_handle_clear(struct kvm *kvm, u64 *its_cmd) +{ + struct vgic_its *its = &kvm->arch.vgic.its; + u32 device_id; + u32 event_id; + struct its_itte *itte; + int ret = 0; + + device_id = its_cmd_get_deviceid(its_cmd); + event_id = its_cmd_get_id(its_cmd); + + spin_lock(&its->lock); + + itte = find_itte(kvm, device_id, event_id); + if (!itte) { + ret = E_ITS_CLEAR_UNMAPPED_INTERRUPT; + goto out_unlock; + } + + if (itte->collection) + __clear_bit(itte->collection->target_addr, itte->pending); + +out_unlock: + spin_unlock(&its->lock); + return ret; +} + +/* The INV command syncs the pending bit from the memory tables. */ +static int vits_cmd_handle_inv(struct kvm *kvm, u64 *its_cmd) +{ + struct vgic_dist *dist = &kvm->arch.vgic; + u32 device_id; + u32 event_id; + struct its_itte *itte, *new_itte; + gpa_t propbase; + int ret; + u8 prop; + + device_id = its_cmd_get_deviceid(its_cmd); + event_id = its_cmd_get_id(its_cmd); + + spin_lock(&dist->its.lock); + itte = find_itte(kvm, device_id, event_id); + spin_unlock(&dist->its.lock); + if (!itte) + return E_ITS_INV_UNMAPPED_INTERRUPT; + + /* + * We cannot read from guest memory inside the spinlock, so we + * need to re-read our tables to learn whether the LPI number we are + * using is still valid. + */ + do { + propbase = BASER_BASE_ADDRESS(dist->propbaser); + ret = kvm_read_guest(kvm, propbase + itte->lpi - GIC_LPI_OFFSET, + &prop, 1); + if (ret) + return ret; + + spin_lock(&dist->its.lock); + new_itte = find_itte(kvm, device_id, event_id); + if (new_itte->lpi != itte->lpi) { + itte = new_itte; + spin_unlock(&dist->its.lock); + continue; + } + update_lpi_config(kvm, itte, prop); + spin_unlock(&dist->its.lock); + } while (0); + return 0; +} + +/* The INVALL command requests flushing of all IRQ data in this collection. */ +static int vits_cmd_handle_invall(struct kvm *kvm, u64 *its_cmd) +{ + u32 coll_id = its_cmd_get_collection(its_cmd); + struct its_collection *collection; + struct kvm_vcpu *vcpu; + + collection = find_collection(kvm, coll_id); + if (!collection) + return E_ITS_INVALL_UNMAPPED_COLLECTION; + + vcpu = kvm_get_vcpu(kvm, collection->target_addr); + + its_update_lpis_configuration(kvm); + its_sync_lpi_pending_table(vcpu); + + return 0; +} + +/* The MOVALL command moves all IRQs from one redistributor to another. */ +static int vits_cmd_handle_movall(struct kvm *kvm, u64 *its_cmd) +{ + struct vgic_its *its = &kvm->arch.vgic.its; + u32 target1_addr = its_cmd_get_target_addr(its_cmd); + u32 target2_addr = its_cmd_mask_field(its_cmd, 3, 16, 32); + struct its_collection *collection; + struct its_device *device; + struct its_itte *itte; + + if (target1_addr >= atomic_read(&kvm->online_vcpus) || + target2_addr >= atomic_read(&kvm->online_vcpus)) + return E_ITS_MOVALL_PROCNUM_OOR; + + if (target1_addr == target2_addr) + return 0; + + spin_lock(&its->lock); + for_each_lpi(device, itte, kvm) { + /* remap all collections mapped to target address 1 */ + collection = itte->collection; + if (collection && collection->target_addr == target1_addr) + collection->target_addr = target2_addr; + + /* move pending state if LPI is affected */ + if (test_and_clear_bit(target1_addr, itte->pending)) + __set_bit(target2_addr, itte->pending); + } + + spin_unlock(&its->lock); + return 0; +} + static int vits_handle_command(struct kvm_vcpu *vcpu, u64 *its_cmd) { - return -ENODEV; + u8 cmd = its_cmd_get_command(its_cmd); + int ret = -ENODEV; + + switch (cmd) { + case GITS_CMD_MAPD: + ret = vits_cmd_handle_mapd(vcpu->kvm, its_cmd); + break; + case GITS_CMD_MAPC: + ret = vits_cmd_handle_mapc(vcpu->kvm, its_cmd); + break; + case GITS_CMD_MAPI: + ret = vits_cmd_handle_mapi(vcpu->kvm, its_cmd, cmd); + break; + case GITS_CMD_MAPTI: + ret = vits_cmd_handle_mapi(vcpu->kvm, its_cmd, cmd); + break; + case GITS_CMD_MOVI: + ret = vits_cmd_handle_movi(vcpu->kvm, its_cmd); + break; + case GITS_CMD_DISCARD: + ret = vits_cmd_handle_discard(vcpu->kvm, its_cmd); + break; + case GITS_CMD_CLEAR: + ret = vits_cmd_handle_clear(vcpu->kvm, its_cmd); + break; + case GITS_CMD_MOVALL: + ret = vits_cmd_handle_movall(vcpu->kvm, its_cmd); + break; + case GITS_CMD_INV: + ret = vits_cmd_handle_inv(vcpu->kvm, its_cmd); + break; + case GITS_CMD_INVALL: + ret = vits_cmd_handle_invall(vcpu->kvm, its_cmd); + break; + case GITS_CMD_SYNC: + /* we ignore this command: we are in sync all of the time */ + ret = 0; + break; + } + + return ret; }

static bool handle_mmio_gits_cbaser(struct kvm_vcpu *vcpu, @@ -554,6 +1048,7 @@ void vits_destroy(struct kvm *kvm) list_for_each_safe(cur, temp, &dev->itt) { itte = (container_of(cur, struct its_itte, itte_list)); list_del(cur); + kfree(itte->pending); kfree(itte); } list_del(dev_cur); diff --git a/virt/kvm/arm/its-emul.h b/virt/kvm/arm/its-emul.h index cbc3877..830524a 100644 --- a/virt/kvm/arm/its-emul.h +++ b/virt/kvm/arm/its-emul.h @@ -39,4 +39,15 @@ void vits_destroy(struct kvm *kvm); bool vits_queue_lpis(struct kvm_vcpu *vcpu); void vits_unqueue_lpi(struct kvm_vcpu *vcpu, int irq);

+#define E_ITS_MOVI_UNMAPPED_INTERRUPT 0x010107 +#define E_ITS_MOVI_UNMAPPED_COLLECTION 0x010109 +#define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507 +#define E_ITS_MAPC_PROCNUM_OOR 0x010902 +#define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04 +#define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06 +#define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07 +#define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09 +#define E_ITS_MOVALL_PROCNUM_OOR 0x010e01 +#define E_ITS_DISCARD_UNMAPPED_INTERRUPT 0x010f07 + #endif

From: Andre Przywara andre.przywara@arm.com

If userspace has provided a base address for the ITS register frame, we enable the bits that advertise LPIs in the GICv3. When the guest has enabled LPIs and the ITS, we enable the emulation part by initializing the ITS data structures and trapping on ITS register frame accesses by the guest. Also we enable the KVM_SIGNAL_MSI feature to allow userland to inject MSIs into the guest. Not having enabled the ITS emulation will lead to a -ENODEV when trying to inject a MSI.

Signed-off-by: Andre Przywara andre.przywara@arm.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- Documentation/virtual/kvm/api.txt | 2 +- arch/arm64/kvm/Kconfig | 1 + arch/arm64/kvm/reset.c | 6 ++++++ include/kvm/arm_vgic.h | 6 ++++++ virt/kvm/arm/its-emul.c | 10 +++++++++- virt/kvm/arm/vgic-v3-emul.c | 20 ++++++++++++++------ virt/kvm/arm/vgic.c | 8 ++++++++ 7 files changed, 45 insertions(+), 8 deletions(-)

diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index cb04095..1b53155 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -2134,7 +2134,7 @@ after pausing the vcpu, but before it is resumed. 4.71 KVM_SIGNAL_MSI

Capability: KVM_CAP_SIGNAL_MSI -Architectures: x86 +Architectures: x86 arm64 Type: vm ioctl Parameters: struct kvm_msi (in) Returns: >0 on delivery, 0 if guest blocked the MSI, and -1 on error diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig index bfffe8f..ff9722f 100644 --- a/arch/arm64/kvm/Kconfig +++ b/arch/arm64/kvm/Kconfig @@ -31,6 +31,7 @@ config KVM select KVM_VFIO select HAVE_KVM_EVENTFD select HAVE_KVM_IRQFD + select HAVE_KVM_MSI ---help--- Support hosting virtualized guest machines.

diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c index 866502b..aff209e 100644 --- a/arch/arm64/kvm/reset.c +++ b/arch/arm64/kvm/reset.c @@ -64,6 +64,12 @@ int kvm_arch_dev_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_ARM_EL1_32BIT: r = cpu_has_32bit_el1(); break; + case KVM_CAP_MSI_DEVID: + if (!kvm) + r = -EINVAL; + else + r = kvm->arch.vgic.msis_require_devid; + break; default: r = 0; } diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 9e1abf9..f50081c 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -162,6 +162,7 @@ struct vgic_io_device {

struct vgic_its { bool enabled; + struct vgic_io_device iodev; spinlock_t lock; u64 cbaser; int creadr; @@ -180,6 +181,9 @@ struct vgic_dist { /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */ u32 vgic_model;

+ /* Do injected MSIs require an additional device ID? */ + bool msis_require_devid; + int nr_cpus; int nr_irqs;

@@ -371,4 +375,6 @@ static inline int vgic_v3_probe(struct device_node *vgic_node, } #endif

+int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi); + #endif diff --git a/virt/kvm/arm/its-emul.c b/virt/kvm/arm/its-emul.c index a1c12bb..b6caefd 100644 --- a/virt/kvm/arm/its-emul.c +++ b/virt/kvm/arm/its-emul.c @@ -1073,6 +1073,7 @@ int vits_init(struct kvm *kvm) { struct vgic_dist *dist = &kvm->arch.vgic; struct vgic_its *its = &dist->its; + int ret;

dist->pendbaser = kmalloc(sizeof(u64) * dist->nr_cpus, GFP_KERNEL); if (!dist->pendbaser) @@ -1087,9 +1088,16 @@ int vits_init(struct kvm *kvm) INIT_LIST_HEAD(&its->device_list); INIT_LIST_HEAD(&its->collection_list);

+ ret = vgic_register_kvm_io_dev(kvm, dist->vgic_its_base, + KVM_VGIC_V3_ITS_SIZE, vgicv3_its_ranges, + -1, &its->iodev); + if (ret) + return ret; + its->enabled = false; + dist->msis_require_devid = true;

- return -ENXIO; + return 0; }

void vits_destroy(struct kvm *kvm) diff --git a/virt/kvm/arm/vgic-v3-emul.c b/virt/kvm/arm/vgic-v3-emul.c index 30bf703..9fd1238 100644 --- a/virt/kvm/arm/vgic-v3-emul.c +++ b/virt/kvm/arm/vgic-v3-emul.c @@ -8,7 +8,6 @@ * * Limitations of the emulation: * (RAZ/WI: read as zero, write ignore, RAO/WI: read as one, write ignore) - * - We do not support LPIs (yet). TYPER.LPIS is reported as 0 and is RAZ/WI. * - We do not support the message based interrupts (MBIs) triggered by * writes to the GICD_{SET,CLR}SPI_* registers. TYPER.MBIS is reported as 0. * - We do not support the (optional) backwards compatibility feature. @@ -87,10 +86,10 @@ static bool handle_mmio_ctlr(struct kvm_vcpu *vcpu, /* * As this implementation does not provide compatibility * with GICv2 (ARE==1), we report zero CPUs in bits [5..7]. - * Also LPIs and MBIs are not supported, so we set the respective bits to 0. - * Also we report at most 2**10=1024 interrupt IDs (to match 1024 SPIs). + * Also we report at most 2**10=1024 interrupt IDs (to match 1024 SPIs) + * and provide 16 bits worth of LPI number space (to give 8192 LPIs). */ -#define INTERRUPT_ID_BITS 10 +#define INTERRUPT_ID_BITS_SPIS 10 static bool handle_mmio_typer(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio, phys_addr_t offset) { @@ -98,7 +97,12 @@ static bool handle_mmio_typer(struct kvm_vcpu *vcpu,

reg = (min(vcpu->kvm->arch.vgic.nr_irqs, 1024) >> 5) - 1;

- reg |= (INTERRUPT_ID_BITS - 1) << 19; + if (vgic_has_its(vcpu->kvm)) { + reg |= GICD_TYPER_LPIS; + reg |= (INTERRUPT_ID_BITS_ITS - 1) << 19; + } else { + reg |= (INTERRUPT_ID_BITS_SPIS - 1) << 19; + }

vgic_reg_access(mmio, &reg, offset, ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); @@ -543,7 +547,9 @@ static bool handle_mmio_ctlr_redist(struct kvm_vcpu *vcpu, vgic_reg_access(mmio, &reg, offset, ACCESS_READ_VALUE | ACCESS_WRITE_VALUE); if (!dist->lpis_enabled && (reg & GICR_CTLR_ENABLE_LPIS)) { - /* Eventually do something */ + vgic_enable_lpis(vcpu); + dist->lpis_enabled = true; + return true; } return false; } @@ -570,6 +576,8 @@ static bool handle_mmio_typer_redist(struct kvm_vcpu *vcpu, reg = redist_vcpu->vcpu_id << 8; if (target_vcpu_id == atomic_read(&vcpu->kvm->online_vcpus) - 1) reg |= GICR_TYPER_LAST; + if (vgic_has_its(vcpu->kvm)) + reg |= GICR_TYPER_PLPIS; vgic_reg_access(mmio, &reg, offset, ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED); return false; diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 9dfd094..081a1ef 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -2246,3 +2246,11 @@ int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, { return 0; } + +int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi) +{ + if (kvm->arch.vgic.vm_ops.inject_msi) + return kvm->arch.vgic.vm_ops.inject_msi(kvm, msi); + else + return -ENODEV; +}

From: Eric Auger eric.auger@linaro.org

Extend kvm_kernel_irq_routing_entry to transport devid. This is needed for ARM. Its validity depends on the routing type entry.

Signed-off-by: Eric Auger eric.auger@linaro.org

---

v1 -> v2: replace msi_msg field by a struct composed of msi_msg and devid

RFC -> PATCH: - reword the commit message after change in first patch (uapi)

Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- include/linux/kvm_host.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 05e99b8..d2f7c86 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -321,7 +321,10 @@ struct kvm_kernel_irq_routing_entry { unsigned irqchip; unsigned pin; } irqchip; - struct msi_msg msi; + struct { + struct msi_msg msi; + u32 devid; + }; struct kvm_s390_adapter_int adapter; }; struct hlist_node link;

From: Eric Auger eric.auger@linaro.org

This patch adds compilation and link against irqchip.

On ARM, irqchip routing is not really useful since there is a single irqchip. However main motivation behind using irqchip code is to enable MSI routing code. With the support of in-kernel GICv3 ITS emulation, it now seems to be a MUST HAVE requirement.

Functions previously implemented in vgic.c and substitute to more complex irqchip implementation are removed:

- kvm_send_userspace_msi - kvm_irq_map_chip_pin - kvm_set_irq - kvm_irq_map_gsi.

They implemented a kernel default identity GSI routing. This is now replaced by user-side provided routing.

Routing standard hooks are now implemented in vgic: - kvm_set_routing_entry - kvm_set_irq - kvm_set_msi

Both HAVE_KVM_IRQCHIP and HAVE_KVM_IRQ_ROUTING are defined. KVM_CAP_IRQ_ROUTING is advertised and KVM_SET_GSI_ROUTING is allowed.

MSI routing is not yet allowed.

Signed-off-by: Eric Auger eric.auger@linaro.org

--- v1 -> v2: - fix bug reported by Andre related to msi.flags and msi.devid setting in kvm_send_userspace_msi - avoid injecting reserved IRQ numbers in vgic_irqfd_set_irq

RFC -> PATCH - reword api.txt: x move MSI routing comments in a subsequent patch, x clearly state GSI routing does not apply to KVM_IRQ_LINE

Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- Documentation/virtual/kvm/api.txt | 12 ++++--- arch/arm/include/asm/kvm_host.h | 2 ++ arch/arm/kvm/Kconfig | 2 ++ arch/arm/kvm/Makefile | 2 +- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/kvm/Kconfig | 2 ++ arch/arm64/kvm/Makefile | 2 +- include/kvm/arm_vgic.h | 2 -- virt/kvm/arm/vgic.c | 69 ++++++++++++++++++++++++++------------- virt/kvm/irqchip.c | 2 ++ 10 files changed, 65 insertions(+), 31 deletions(-)

diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 3094139..459da31 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -1421,13 +1421,16 @@ KVM_ASSIGN_DEV_IRQ. Partial deassignment of host or guest IRQ is allowed. 4.52 KVM_SET_GSI_ROUTING

Capability: KVM_CAP_IRQ_ROUTING -Architectures: x86 s390 +Architectures: x86 s390 arm arm64 Type: vm ioctl Parameters: struct kvm_irq_routing (in) Returns: 0 on success, -1 on error

Sets the GSI routing table entries, overwriting any previously set entries.

+On arm/arm64, GSI routing has the following limitation: +- GSI routing does not apply to KVM_IRQ_LINE but only to KVM_IRQFD. + struct kvm_irq_routing { __u32 nr; __u32 flags; @@ -2339,9 +2342,10 @@ Note that closing the resamplefd is not sufficient to disable the irqfd. The KVM_IRQFD_FLAG_RESAMPLE is only necessary on assignment and need not be specified with KVM_IRQFD_FLAG_DEASSIGN.

-On ARM/ARM64, the gsi field in the kvm_irqfd struct specifies the Shared -Peripheral Interrupt (SPI) index, such that the GIC interrupt ID is -given by gsi + 32. +On arm/arm64, gsi routing being supported, the following can happen: +- in case no routing entry is associated to this gsi, injection fails +- in case the gsi is associated to an irqchip routing entry, + irqchip.pin + 32 corresponds to the injected SPI ID.

4.76 KVM_PPC_ALLOCATE_HTAB

diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h index 56cac05..9ced147 100644 --- a/arch/arm/include/asm/kvm_host.h +++ b/arch/arm/include/asm/kvm_host.h @@ -42,6 +42,8 @@

#define KVM_VCPU_MAX_FEATURES 2

+#define KVM_IRQCHIP_NUM_PINS 988 /* 1020 -32 is the number of SPI */ + #include <kvm/arm_vgic.h>

u32 *kvm_vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num, u32 mode); diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig index bfb915d..151e710 100644 --- a/arch/arm/kvm/Kconfig +++ b/arch/arm/kvm/Kconfig @@ -31,6 +31,8 @@ config KVM select KVM_VFIO select HAVE_KVM_EVENTFD select HAVE_KVM_IRQFD + select HAVE_KVM_IRQCHIP + select HAVE_KVM_IRQ_ROUTING depends on ARM_VIRT_EXT && ARM_LPAE && ARM_ARCH_TIMER ---help--- Support hosting virtualized guest machines. diff --git a/arch/arm/kvm/Makefile b/arch/arm/kvm/Makefile index c5eef02c..1a8f48a 100644 --- a/arch/arm/kvm/Makefile +++ b/arch/arm/kvm/Makefile @@ -15,7 +15,7 @@ AFLAGS_init.o := -Wa,-march=armv7-a$(plus_virt) AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)

KVM := ../../../virt/kvm -kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o $(KVM)/vfio.o +kvm-arm-y = $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o $(KVM)/vfio.o $(KVM)/irqchip.o

obj-y += kvm-arm.o init.o interrupts.o obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 8d78a72..ff007cf 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -44,6 +44,7 @@ #include <kvm/arm_arch_timer.h>

#define KVM_VCPU_MAX_FEATURES 3 +#define KVM_IRQCHIP_NUM_PINS 988 /* 1020 -32 is the number of SPI */

int __attribute_const__ kvm_target_cpu(void); int kvm_reset_vcpu(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig index ff9722f..1a9900d 100644 --- a/arch/arm64/kvm/Kconfig +++ b/arch/arm64/kvm/Kconfig @@ -32,6 +32,8 @@ config KVM select HAVE_KVM_EVENTFD select HAVE_KVM_IRQFD select HAVE_KVM_MSI + select HAVE_KVM_IRQCHIP + select HAVE_KVM_IRQ_ROUTING ---help--- Support hosting virtualized guest machines.

diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile index 9803307..90a08457 100644 --- a/arch/arm64/kvm/Makefile +++ b/arch/arm64/kvm/Makefile @@ -11,7 +11,7 @@ ARM=../../../arch/arm/kvm

obj-$(CONFIG_KVM_ARM_HOST) += kvm.o

-kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o $(KVM)/vfio.o +kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/kvm_main.o $(KVM)/coalesced_mmio.o $(KVM)/eventfd.o $(KVM)/vfio.o $(KVM)/irqchip.o kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/arm.o $(ARM)/mmu.o $(ARM)/mmio.o kvm-$(CONFIG_KVM_ARM_HOST) += $(ARM)/psci.o $(ARM)/perf.o

diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index f50081c..1b370a0 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -375,6 +375,4 @@ static inline int vgic_v3_probe(struct device_node *vgic_node, } #endif

-int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi); - #endif diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 081a1ef..e38a0de 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -2215,42 +2215,65 @@ out_free_irq: return ret; }

-int kvm_irq_map_gsi(struct kvm *kvm, - struct kvm_kernel_irq_routing_entry *entries, - int gsi) +int vgic_irqfd_set_irq(struct kvm_kernel_irq_routing_entry *e, + struct kvm *kvm, int irq_source_id, + int level, bool line_status) { - return 0; -} - -int kvm_irq_map_chip_pin(struct kvm *kvm, unsigned irqchip, unsigned pin) -{ - return pin; -} - -int kvm_set_irq(struct kvm *kvm, int irq_source_id, - u32 irq, int level, bool line_status) -{ - unsigned int spi = irq + VGIC_NR_PRIVATE_IRQS; + unsigned int spi_id = e->irqchip.pin + VGIC_NR_PRIVATE_IRQS;

- trace_kvm_set_irq(irq, level, irq_source_id); + trace_kvm_set_irq(spi_id, level, irq_source_id);

BUG_ON(!vgic_initialized(kvm));

- return kvm_vgic_inject_irq(kvm, 0, spi, level); + if (spi_id > min(kvm->arch.vgic.nr_irqs, 1020)) + return -EINVAL; + return kvm_vgic_inject_irq(kvm, 0, spi_id, level); +} + +/** + * Populates a kvm routing entry from a user routing entry + * @e: kvm internal formatted entry + * @ue: user api formatted entry + * return 0 on success, -EINVAL on errors. + */ +int kvm_set_routing_entry(struct kvm_kernel_irq_routing_entry *e, + const struct kvm_irq_routing_entry *ue) +{ + int r = -EINVAL; + + switch (ue->type) { + case KVM_IRQ_ROUTING_IRQCHIP: + e->set = vgic_irqfd_set_irq; + e->irqchip.irqchip = ue->u.irqchip.irqchip; + e->irqchip.pin = ue->u.irqchip.pin; + if ((e->irqchip.pin >= KVM_IRQCHIP_NUM_PINS) || + (e->irqchip.irqchip >= KVM_NR_IRQCHIPS)) + goto out; + break; + default: + goto out; + } + r = 0; +out: + return r; }

-/* MSI not implemented yet */ int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e, struct kvm *kvm, int irq_source_id, int level, bool line_status) { - return 0; -} + struct kvm_msi msi; + + msi.address_lo = e->msi.address_lo; + msi.address_hi = e->msi.address_hi; + msi.data = e->msi.data; + if (e->type == KVM_IRQ_ROUTING_EXTENDED_MSI) { + msi.devid = e->devid; + msi.flags = KVM_MSI_VALID_DEVID; + }

-int kvm_send_userspace_msi(struct kvm *kvm, struct kvm_msi *msi) -{ if (kvm->arch.vgic.vm_ops.inject_msi) - return kvm->arch.vgic.vm_ops.inject_msi(kvm, msi); + return kvm->arch.vgic.vm_ops.inject_msi(kvm, &msi); else return -ENODEV; } diff --git a/virt/kvm/irqchip.c b/virt/kvm/irqchip.c index e678f8a..f26cadd 100644 --- a/virt/kvm/irqchip.c +++ b/virt/kvm/irqchip.c @@ -29,7 +29,9 @@ #include <linux/srcu.h> #include <linux/export.h> #include <trace/events/kvm.h> +#if !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) #include "irq.h" +#endif

struct kvm_irq_routing_table { int chip[KVM_NR_IRQCHIPS][KVM_IRQCHIP_NUM_PINS];

From: Eric Auger eric.auger@linaro.org

Up to now, only irqchip routing entries could be set. This patch adds the capability to insert MSI routing entries, with or without device id. Although standard MSI entries can be set, their injection still is not supported. For ARM64, let's also increase KVM_MAX_IRQ_ROUTES to 4096: include SPI irqchip flat routes plus MSI routes. In the future this might be extended.

The new MSI routing entry type also must be managed similarly to legacy KVM_IRQ_ROUTING_MSI in eventfd irqfd_wakeup and irqfd_update.

Signed-off-by: Eric Auger eric.auger@linaro.org

---

v1 -> v2: - adapt to new routing entry types

RFC -> PATCH: - move api MSI routing updates into that patch file - use new devid field of user api struct

Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- Documentation/virtual/kvm/api.txt | 10 ++++++++++ include/linux/kvm_host.h | 2 ++ virt/kvm/arm/vgic.c | 13 +++++++++++++ virt/kvm/eventfd.c | 6 ++++-- 4 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 459da31..8a772e0 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -1431,6 +1431,11 @@ Sets the GSI routing table entries, overwriting any previously set entries. On arm/arm64, GSI routing has the following limitation: - GSI routing does not apply to KVM_IRQ_LINE but only to KVM_IRQFD.

+On arm/arm64, MSI routing through in-kernel GICv3 ITS must use +KVM_IRQ_ROUTING_EXTENDED_MSI routing type and device ID must be set +in msi struct. Otherwise, KVM_IRQ_ROUTING_MSI must be used without +populating the msi devid field. + struct kvm_irq_routing { __u32 nr; __u32 flags; @@ -2346,6 +2351,11 @@ On arm/arm64, gsi routing being supported, the following can happen: - in case no routing entry is associated to this gsi, injection fails - in case the gsi is associated to an irqchip routing entry, irqchip.pin + 32 corresponds to the injected SPI ID. +- in case the gsi is associated to an MSI routing entry, + * without GICv3 ITS in-kernel emulation, MSI data matches the SPI ID + of the injected SPI + * with GICv3 ITS in-kernel emulation, the MSI message and device ID + are translated into an LPI.

4.76 KVM_PPC_ALLOCATE_HTAB

diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index d2f7c86..f580f4b 100644 --- a/include/linux/kvm_host.h +++ b/include/linux/kvm_host.h @@ -994,6 +994,8 @@ static inline int mmu_notifier_retry(struct kvm *kvm, unsigned long mmu_seq)

#ifdef CONFIG_S390 #define KVM_MAX_IRQ_ROUTES 4096 //FIXME: we can have more than that... +#elif defined(CONFIG_ARM64) +#define KVM_MAX_IRQ_ROUTES 4096 #else #define KVM_MAX_IRQ_ROUTES 1024 #endif diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c index 12391a9..ebf5073 100644 --- a/virt/kvm/arm/vgic.c +++ b/virt/kvm/arm/vgic.c @@ -2252,6 +2252,19 @@ int kvm_set_routing_entry(struct kvm_kernel_irq_routing_entry *e, (e->irqchip.irqchip >= KVM_NR_IRQCHIPS)) goto out; break; + case KVM_IRQ_ROUTING_MSI: + e->set = kvm_set_msi; + e->msi.address_lo = ue->u.msi.address_lo; + e->msi.address_hi = ue->u.msi.address_hi; + e->msi.data = ue->u.msi.data; + break; + case KVM_IRQ_ROUTING_EXTENDED_MSI: + e->set = kvm_set_msi; + e->msi.address_lo = ue->u.msi.address_lo; + e->msi.address_hi = ue->u.msi.address_hi; + e->msi.data = ue->u.msi.data; + e->devid = ue->u.msi.devid; + break; default: goto out; } diff --git a/virt/kvm/eventfd.c b/virt/kvm/eventfd.c index 9ff4193..d76d05d 100644 --- a/virt/kvm/eventfd.c +++ b/virt/kvm/eventfd.c @@ -238,7 +238,8 @@ irqfd_wakeup(wait_queue_t *wait, unsigned mode, int sync, void *key) irq = irqfd->irq_entry; } while (read_seqcount_retry(&irqfd->irq_entry_sc, seq)); /* An event has been signaled, inject an interrupt */ - if (irq.type == KVM_IRQ_ROUTING_MSI) + if (irq.type == KVM_IRQ_ROUTING_MSI || + irq.type == KVM_IRQ_ROUTING_EXTENDED_MSI) kvm_set_msi(&irq, kvm, KVM_USERSPACE_IRQ_SOURCE_ID, 1, false); else @@ -294,7 +295,8 @@ static void irqfd_update(struct kvm *kvm, struct _irqfd *irqfd) e = entries; for (i = 0; i < n_entries; ++i, ++e) { /* Only fast-path MSI. */ - if (e->type == KVM_IRQ_ROUTING_MSI) + if (e->type == KVM_IRQ_ROUTING_MSI || + e->type == KVM_IRQ_ROUTING_EXTENDED_MSI) irqfd->irq_entry = *e; }

From: Andrew Pinski apinski@cavium.com

On some cores, udiv with a large value is slow, expand instead the division out to be what GCC would have generated for the divide by 1000.

Signed-off-by: Andrew Pinski apinski@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/kernel/vdso/gettimeofday.S | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kernel/vdso/gettimeofday.S b/arch/arm64/kernel/vdso/gettimeofday.S index efa79e8..e5caef9 100644 --- a/arch/arm64/kernel/vdso/gettimeofday.S +++ b/arch/arm64/kernel/vdso/gettimeofday.S @@ -64,10 +64,22 @@ ENTRY(__kernel_gettimeofday) bl __do_get_tspec seqcnt_check w9, 1b

- /* Convert ns to us. */ - mov x13, #1000 - lsl x13, x13, x12 - udiv x11, x11, x13 + /* Undo the shift. */ + lsr x11, x11, x12 + + /* Convert ns to us (division by 1000 by using multiply high). + * This is how GCC converts the division by 1000 into. + * This is faster than divide on most cores. + */ + mov x13, 63439 + movk x13, 0xe353, lsl 16 + lsr x11, x11, 3 + movk x13, 0x9ba5, lsl 32 + movk x13, 0x20c4, lsl 48 + /* x13 = 0x20c49ba5e353f7cf */ + umulh x11, x11, x13 + lsr x11, x11, 4 + stp x10, x11, [x0, #TVAL_TV_SEC] 2: /* If tz is NULL, return 0. */

From: Andrew Pinski apinski@cavium.com

For high core counts, we want to add a delay when current serving tick is "far" away from our ticket.

Signed-off-by: Andrew Pinski apinski@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/include/asm/spinlock.h | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/include/asm/spinlock.h b/arch/arm64/include/asm/spinlock.h index cee1287..d867547 100644 --- a/arch/arm64/include/asm/spinlock.h +++ b/arch/arm64/include/asm/spinlock.h @@ -51,10 +51,31 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) * unlock before the exclusive load. */ " sevl\n" -"2: wfe\n" + /* Delay if our ticket is not the next ticket. */ +" uxth %w2, %w0\n" +" lsr %w0, %w0, 16\n" + /* %w2 is the difference between our ticket and the current ticket. */ +"2: sub %w2, %w0, %w2\n" + /* If the tickets have wrapped, then we need to add USHORT_MAX. */ +" cmp %w2, wzr\n" +" b.lt 5f\n" +"6: sub %w2, %w2, 1\n" +" cbz %w2, 7f\n" + /* Multiply by 64, a good estimate of how long an lock/unlock will take. */ +" lsl %w2, %w2, 6\n" + /* Spin until we get 0. */ +"4: sub %w2, %w2, 1\n" +" cbnz %w2, 4b\n" + /* Wait for event, we might not be the current ticket. */ +"7: wfe\n" " ldaxrh %w2, %4\n" -" eor %w1, %w2, %w0, lsr #16\n" +" eor %w1, %w2, %w0\n" " cbnz %w1, 2b\n" +" b 3f\n" + /* Wrap case, add USHORT_MAX to wrap around again. */ +"5: mov %w1, 0xffff\n" +" add %w2, %w2, %w1\n" +" b 7b\n" /* We got the lock. Critical section starts here. */ "3:" : "=&r" (lockval), "=&r" (newval), "=&r" (tmp), "+Q" (*lock)

From: Andrew Pinski apinski@cavium.com

Adding a check for the cache line size is not much overhead. Special case 128 byte cache line size. This improves copy_page by 85% on ThunderX compared to the original implementation.

For LMBench, it improves between 4-10%.

Signed-off-by: Andrew Pinski apinski@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/lib/copy_page.S | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)

diff --git a/arch/arm64/lib/copy_page.S b/arch/arm64/lib/copy_page.S index 512b9a7..24c72f2 100644 --- a/arch/arm64/lib/copy_page.S +++ b/arch/arm64/lib/copy_page.S @@ -27,6 +27,12 @@ * x1 - src */ ENTRY(copy_page) + /* Special case 128 byte or more cache lines */ + mrs x2, dczid_el0 + and w2, w2, #0xf + cmp w2, 5 + b.ge 2f + /* Assume cache line size is 64 bytes. */ prfm pldl1strm, [x1, #64] 1: ldp x2, x3, [x1] @@ -40,6 +46,32 @@ ENTRY(copy_page) stnp x6, x7, [x0, #32] stnp x8, x9, [x0, #48] add x0, x0, #64 + tst x1, #(PAGE_SIZE - 1) + b.ne 1b + ret +2: + /* The cache line size is at least 128 bytes. */ + prfm pldl1strm, [x1, #128] +1: prfm pldl1strm, [x1, #256] + ldp x2, x3, [x1] + ldp x4, x5, [x1, #16] + ldp x6, x7, [x1, #32] + ldp x8, x9, [x1, #48] + stnp x2, x3, [x0] + stnp x4, x5, [x0, #16] + stnp x6, x7, [x0, #32] + stnp x8, x9, [x0, #48] + + ldp x2, x3, [x1, #64] + ldp x4, x5, [x1, #80] + ldp x6, x7, [x1, #96] + ldp x8, x9, [x1, #112] + add x1, x1, #128 + stnp x2, x3, [x0, #64] + stnp x4, x5, [x0, #80] + stnp x6, x7, [x0, #96] + stnp x8, x9, [x0, #112] + add x0, x0, #128 tst x1, #(PAGE_SIZE - 1) b.ne 1b ret

From: Craig Magina craig.magina@canonical.com

Using the glibc cortex string work work authored by Linaro as base to create new copy to/from user kernel routine.

Iperf performance increase: -l (size) 1 core result Optimized 64B 44-51Mb/s 1500B 4.9Gb/s 30000B 16.2Gb/s Original 64B 34-50.7Mb/s 1500B 4.7Gb/s 30000B 14.5Gb/s

BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1400349

Note there was one change I did to move around tst to be right next to the branch for better optimization for ThunderX.

Signed-off-by: Craig Magina craig.magina@canonical.com Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/lib/copy_template.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/lib/copy_template.S b/arch/arm64/lib/copy_template.S index c07eea6..bdce432 100644 --- a/arch/arm64/lib/copy_template.S +++ b/arch/arm64/lib/copy_template.S @@ -169,9 +169,9 @@ D_h .req x14 USER(12f, stp B_l, B_h, [dst, #16]) USER(12f, stp C_l, C_h, [dst, #32]) USER(12f, stp D_l, D_h, [dst, #48]) - tst count, #0x3f add src, src, #64 add dst, dst, #64 + tst count, #0x3f b.ne .Ltail63 b .Lsuccess

From: Graeme Gregory graeme.gregory@linaro.org

This is a standard platform device to resources are converted in the ACPI core in the same fasion as DT resources. For the other DT provided information there is _DSD for ACPI.

Signed-off-by: Graeme Gregory graeme.gregory@linaro.org Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/net/ethernet/smsc/smsc911x.c | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+)

diff --git a/drivers/net/ethernet/smsc/smsc911x.c b/drivers/net/ethernet/smsc/smsc911x.c index 959aeea..9161f0a 100644 --- a/drivers/net/ethernet/smsc/smsc911x.c +++ b/drivers/net/ethernet/smsc/smsc911x.c @@ -31,6 +31,7 @@

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

+#include <linux/acpi.h> #include <linux/crc32.h> #include <linux/clk.h> #include <linux/delay.h> @@ -2412,9 +2413,36 @@ static inline int smsc911x_probe_config_dt( } #endif /* CONFIG_OF */

+#ifdef CONFIG_ACPI +/* Configure some sensible defaults for ACPI mode */ +static int smsc911x_probe_config_acpi(struct smsc911x_platform_config *config, + acpi_handle *ahandle) +{ + if (!ahandle) + return -ENOSYS; + + config->phy_interface = PHY_INTERFACE_MODE_MII; + + config->flags |= SMSC911X_USE_32BIT; + + config->irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH; + + config->irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL; + + return 0; +} +#else +static int smsc911x_probe_config_acpi(struct smsc911x_platform_config *config, + acpi_handle *ahandle) +{ + return -ENOSYS; +} +#endif /* CONFIG_ACPI */ + static int smsc911x_drv_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + acpi_handle *ahandle = ACPI_HANDLE(&pdev->dev); struct net_device *dev; struct smsc911x_data *pdata; struct smsc911x_platform_config *config = dev_get_platdata(&pdev->dev); @@ -2479,6 +2507,9 @@ static int smsc911x_drv_probe(struct platform_device *pdev) }

retval = smsc911x_probe_config_dt(&pdata->config, np); + if (retval) + retval = smsc911x_probe_config_acpi(&pdata->config, ahandle); + if (retval && config) { /* copy config parameters across to pdata */ memcpy(&pdata->config, config, sizeof(pdata->config)); @@ -2654,6 +2685,12 @@ static const struct of_device_id smsc911x_dt_ids[] = { MODULE_DEVICE_TABLE(of, smsc911x_dt_ids); #endif

+static const struct acpi_device_id smsc911x_acpi_ids[] = { + { "LNRO001B", }, + { "ARMH9118", }, + { } +}; + static struct platform_driver smsc911x_driver = { .probe = smsc911x_drv_probe, .remove = smsc911x_drv_remove, @@ -2661,6 +2698,7 @@ static struct platform_driver smsc911x_driver = { .name = SMSC_CHIPNAME, .pm = SMSC911X_PM_OPS, .of_match_table = of_match_ptr(smsc911x_dt_ids), + .acpi_match_table = ACPI_PTR(smsc911x_acpi_ids), }, };

From: Graeme Gregory graeme.gregory@linaro.org

Added the match table and pointers for ACPI probing to the driver.

Signed-off-by: Graeme Gregory graeme.gregory@linaro.org Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/virtio/virtio_mmio.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c index 10189b5..9f9f4c3 100644 --- a/drivers/virtio/virtio_mmio.c +++ b/drivers/virtio/virtio_mmio.c @@ -70,8 +70,7 @@ #include <linux/virtio_config.h> #include <linux/virtio_mmio.h> #include <linux/virtio_ring.h> - - +#include <linux/acpi.h>

/* The alignment to use between consumer and producer parts of vring. * Currently hardcoded to the page size. */ @@ -732,12 +731,21 @@ static struct of_device_id virtio_mmio_match[] = { }; MODULE_DEVICE_TABLE(of, virtio_mmio_match);

+#ifdef CONFIG_ACPI +static const struct acpi_device_id virtio_mmio_acpi_match[] = { + { "LNRO0005", }, + { } +}; +MODULE_DEVICE_TABLE(acpi, virtio_mmio_acpi_match); +#endif + static struct platform_driver virtio_mmio_driver = { .probe = virtio_mmio_probe, .remove = virtio_mmio_remove, .driver = { .name = "virtio-mmio", .of_match_table = virtio_mmio_match, + .acpi_match_table = ACPI_PTR(virtio_mmio_acpi_match), }, };

From: Naresh Bhat naresh.bhat@linaro.org

Add match table and pointers for ACPI probing into vexpress-sysreg driver.

vexpress-sysreg is self-contained so it gets resources automatically being platform driver. However, while it is not probed, it still should provides base address so that other related drivers can take advantage of it. Make it possible and find resources based on device HID.

Signed-off-by: Naresh Bhat naresh.bhat@linaro.org Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/mfd/vexpress-sysreg.c | 66 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 63 insertions(+), 3 deletions(-)

diff --git a/drivers/mfd/vexpress-sysreg.c b/drivers/mfd/vexpress-sysreg.c index 8f43ab8..0db1746 100644 --- a/drivers/mfd/vexpress-sysreg.c +++ b/drivers/mfd/vexpress-sysreg.c @@ -22,6 +22,7 @@ #include <linux/slab.h> #include <linux/stat.h> #include <linux/vexpress.h> +#include <linux/acpi.h>

#define SYS_ID 0x000 #define SYS_SW 0x004 @@ -55,15 +56,66 @@

static void __iomem *__vexpress_sysreg_base;

+#ifdef CONFIG_ACPI +static acpi_status check_vexpress_resource(struct acpi_resource *res, + void *data) +{ + struct resource *vexpress_res = data; + + if (!acpi_dev_resource_memory(res, vexpress_res)) + pr_err("Failed to map vexpress memory resource\n"); + + __vexpress_sysreg_base = ioremap(vexpress_res->start, + resource_size(vexpress_res)); + if (__vexpress_sysreg_base) + return AE_CTRL_TERMINATE; + + return AE_OK; +} + +static acpi_status find_vexpress_resource(acpi_handle handle, u32 lvl, + void *context, void **rv) +{ + struct resource *vexpress_res = context; + + acpi_walk_resources(handle, METHOD_NAME__CRS, + check_vexpress_resource, context); + + if (vexpress_res->flags) + return AE_CTRL_TERMINATE; + + return AE_OK; +} + +static void acpi_vexpress_sysreg_base(void) +{ + struct resource vexpress_res; + + acpi_get_devices("LNRO0009", find_vexpress_resource, &vexpress_res, + NULL); +} +#else +static inline void acpi_vexpress_sysreg_base(void) +{ +} +#endif + static void __iomem *vexpress_sysreg_base(void) { - if (!__vexpress_sysreg_base) { - struct device_node *node = of_find_compatible_node(NULL, NULL, - "arm,vexpress-sysreg"); + struct device_node *node; + + if (__vexpress_sysreg_base) + goto ret;

+ node = of_find_compatible_node(NULL, NULL, "arm,vexpress-sysreg"); + if (node) { __vexpress_sysreg_base = of_iomap(node, 0); + goto ret; }

+ acpi_vexpress_sysreg_base(); + +ret: WARN_ON(!__vexpress_sysreg_base);

return __vexpress_sysreg_base; @@ -255,10 +307,18 @@ static const struct of_device_id vexpress_sysreg_match[] = { {}, };

+#ifdef CONFIG_ACPI +static const struct acpi_device_id vexpress_sysreg_acpi_match[] = { + { "LNRO0009", }, + { } +}; +#endif + static struct platform_driver vexpress_sysreg_driver = { .driver = { .name = "vexpress-sysreg", .of_match_table = vexpress_sysreg_match, + .acpi_match_table = ACPI_PTR(vexpress_sysreg_acpi_match), }, .probe = vexpress_sysreg_probe, };

From: Al Stone ahs3@redhat.com

Arm allows for two possible architectural clock sources. One memory mapped and the other coprocessor based. If both timers exist, then the driver waits for both to be probed before registering a clocksource.

Commit c387f07e6205 ("clocksource: arm_arch_timer: Discard unavailable timers correctly") attempted to fix a hang occurring when one of the two possible timers had a device node, but was disabled. In that case, the second probe would never occur and the system would hang without a clocksource being registered.

Unfortunately, incorrect logic in that commit made things worse such that a hang would occur unless both timers had a device node and were enabled. This patch fixes the logic so that we don't wait to probe a second timer unless it exists and is enabled.

Signed-off-by: Mark Salter msalter@redhat.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/clocksource/arm_arch_timer.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 0aa135d..17ad6f4 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -672,10 +672,11 @@ arch_timer_needs_probing(int type, const struct of_device_id *matches) bool needs_probing = false;

dn = of_find_matching_node(NULL, matches); - if (dn && of_device_is_available(dn) && !(arch_timers_present & type)) - needs_probing = true; - of_node_put(dn); - + if (dn) { + if (dn && of_device_is_available(dn) && !(arch_timers_present & type)) + needs_probing = true; + of_node_put(dn); + } return needs_probing; }

From: Tomasz Nowicki tomasz.nowicki@linaro.org

Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/irqchip/irq-gic-v3.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 9c67bda..89dde54 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -790,6 +790,7 @@ static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, }

static const struct irq_domain_ops gic_irq_domain_ops = { + .map = gic_irq_domain_map, .xlate = gic_irq_domain_xlate, .alloc = gic_irq_domain_alloc, .free = gic_irq_domain_free,

From: Tomasz Nowicki tomasz.nowicki@linaro.org

Obtain GICv3+ re-distributor base addresses from MADT subtable, check data integrity and call GICv3 init funtion. GIC drivers probe order: if MADT provides redistributors, try GICv3 driver, otherwise try GICv2.

Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/kernel/acpi.c | 4 +- drivers/irqchip/irq-gic-v3.c | 210 +++++++++++++++++++++++++++++++++++ include/linux/irqchip/arm-gic-acpi.h | 2 + 3 files changed, 215 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c index 26928c4..2f8ca43 100644 --- a/arch/arm64/kernel/acpi.c +++ b/arch/arm64/kernel/acpi.c @@ -251,9 +251,11 @@ void __init acpi_gic_init(void) }

err = acpi_gic_ver < ACPI_MADT_GIC_VER_V3 ? - gic_v2_acpi_init(table) : -ENXIO; + gic_v2_acpi_init(table) : + gic_v3_acpi_init(table); if (err) pr_err("Failed to initialize GIC IRQ controller");

+ early_acpi_os_unmap_memory((char *)table, tbl_size); } diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 622a2f7..db82724 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -22,10 +22,12 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/acpi.h> #include <linux/percpu.h> #include <linux/slab.h>

#include <linux/irqchip/arm-gic-v3.h> +#include <linux/irqchip/arm-gic-acpi.h>

#include <asm/cputype.h> #include <asm/exception.h> @@ -943,3 +945,211 @@ out_unmap_dist:

IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); #endif + +#ifdef CONFIG_ACPI +static struct redist_region *redist_regs; +static u32 redist_regions; +static void __iomem *dist_base; + +static void __iomem * __init +gic_acpi_map_one_redist(u64 redist_base_address) +{ + void __iomem *redist_base; + u64 typer; + u32 reg; + + /* Map RD + SGI pages */ + redist_base = ioremap(redist_base_address, 2 * SZ_64K); + if (!redist_base) + return NULL; + + /* + * Map another two pages VLPI + reserved, if GIC support + * virtual LPI. + */ + reg = readl_relaxed(redist_base + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; + if (reg != 0x30 && reg != 0x40) { /* We're in trouble... */ + pr_warn("No redistributor present @%p\n", redist_base); + iounmap(redist_base); + return NULL; + } + + typer = readq_relaxed(redist_base + GICR_TYPER); + if (typer & GICR_TYPER_VLPIS) { + iounmap(redist_base); + redist_base = ioremap(redist_base_address, 4 * SZ_64K); + } + + return redist_base; +} + +static int __init +gic_acpi_register_redist(u64 redist_base_address, u64 size, int region) +{ + struct redist_region *redist_regs_new; + void __iomem *redist_base; + + redist_regs_new = krealloc(redist_regs, + sizeof(*redist_regs) * (redist_regions + 1), + GFP_KERNEL); + if (!redist_regs_new) { + pr_err("Couldn't allocate resource for GICR region\n"); + return -ENOMEM; + } + + redist_regs = redist_regs_new; + + /* + * Region contains a distinct set of GIC redistributors. Region size + * gives us all info we need to map redistributors properly. + * + * If it is not region, we assume to deal with one redistributor. + * Redistributor size is probeable and depends on GIC version: + * GICv3: RD + SGI pages + * GICv4: RD + SGI + VLPI + reserved pages + */ + if (region) + redist_base = ioremap(redist_base_address, size); + else + redist_base = gic_acpi_map_one_redist(redist_base_address); + + if (!redist_base) { + pr_err("Couldn't map GICR region @%lx\n", + (long int)redist_base_address); + return -ENOMEM; + } + + redist_regs[redist_regions].phys_base = redist_base_address; + redist_regs[redist_regions++].redist_base = redist_base; + return 0; +} + +static int __init +gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_interrupt *processor; + + if (BAD_MADT_ENTRY(header, end)) + return -EINVAL; + + processor = (struct acpi_madt_generic_interrupt *)header; + if (!processor->gicr_base_address) + return -EINVAL; + + return gic_acpi_register_redist(processor->gicr_base_address, 0, 0); +} + +static int __init +gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_redistributor *redist; + + if (BAD_MADT_ENTRY(header, end)) + return -EINVAL; + + redist = (struct acpi_madt_generic_redistributor *)header; + if (!redist->base_address) + return -EINVAL; + + return gic_acpi_register_redist(redist->base_address, + redist->length, 1); +} + +static int __init +gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_distributor *dist; + + dist = (struct acpi_madt_generic_distributor *)header; + + if (BAD_MADT_ENTRY(dist, end)) + return -EINVAL; + + dist_base = ioremap(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE); + if (!dist_base) { + pr_err("Unable to map GICD registers\n"); + return -ENOMEM; + } + + return 0; +} + +int __init +gic_v3_acpi_init(struct acpi_table_header *table) +{ + int count, i, err = 0; + + /* Collect redistributor base addresses */ + count = acpi_parse_entries(ACPI_SIG_MADT, + sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_redist, table, + ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 0); + if (!count) + pr_info("No valid GICR entries exist\n"); + else if (count < 0) { + pr_err("Error during GICR entries parsing\n"); + err = -EINVAL; + goto out_redist_unmap; + } else + goto madt_dist; + + /* + * There might be no GICR structure but we can still obtain + * redistributor collection from GICC subtables. + */ + count = acpi_parse_entries(ACPI_SIG_MADT, + sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_cpu, table, + ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); + if (!count) { + pr_info("No valid GICC entries exist\n"); + return -EINVAL; + } else if (count < 0) { + pr_err("Error during GICC entries parsing\n"); + err = -EINVAL; + goto out_redist_unmap; + } + +madt_dist: + /* + * We assume to parse one distributor entry since ACPI 5.0 spec + * neither support multi-GIC instances nor cascade. + */ + count = acpi_parse_entries(ACPI_SIG_MADT, + sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_distributor, table, + ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); + if (count < 0) { + pr_err("Error during GICD entries parsing\n"); + err = -EINVAL; + goto out_redist_unmap; + } else if (!count) { + pr_err("No valid GICD entries exist\n"); + err = -EINVAL; + goto out_redist_unmap; + } else if (count > 1) { + pr_err("More than one GICD entry detected\n"); + err = -EINVAL; + goto out_redist_unmap; + } + + err = gic_init_bases(dist_base, redist_regs, redist_regions, 0, NULL); + if (err) + goto out_dist_unmap; + + irq_set_default_host(gic_data.domain); + return 0; + +out_dist_unmap: + iounmap(dist_base); +out_redist_unmap: + for (i = 0; i < redist_regions; i++) + if (redist_regs[i].redist_base) + iounmap(redist_regs[i].redist_base); + kfree(redist_regs); + return err; +} +#endif diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h index de3419e..27e77d5 100644 --- a/include/linux/irqchip/arm-gic-acpi.h +++ b/include/linux/irqchip/arm-gic-acpi.h @@ -18,11 +18,13 @@ * from GIC spec. */ #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) +#define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)

struct acpi_table_header;

int gic_v2_acpi_init(struct acpi_table_header *table); +int gic_v3_acpi_init(struct acpi_table_header *table); void acpi_gic_init(void); #else static inline void acpi_gic_init(void) { }

From: Tomasz Nowicki tomasz.nowicki@linaro.org

Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/irqchip/irq-gic-v3-its.c | 34 ++++++++++++++++++++++++++++++++++ drivers/irqchip/irq-gic-v3.c | 2 ++ include/linux/irqchip/arm-gic-acpi.h | 1 + 3 files changed, 37 insertions(+)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index 3b7f352..4814954 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -27,10 +27,12 @@ #include <linux/of_irq.h> #include <linux/of_pci.h> #include <linux/of_platform.h> +#include <linux/acpi.h> #include <linux/percpu.h> #include <linux/slab.h>

#include <linux/irqchip/arm-gic-v3.h> +#include <linux/irqchip/arm-gic-acpi.h>

#include <asm/cacheflush.h> #include <asm/cputype.h> @@ -1651,6 +1653,38 @@ void its_of_probe(struct device_node *node) } }

+#ifdef CONFIG_ACPI +static int __init +gic_acpi_parse_madt_its(struct acpi_subtable_header *header, + const unsigned long end) +{ + struct acpi_madt_generic_translator *its; + + if (BAD_MADT_ENTRY(header, end)) + return -EINVAL; + + its = (struct acpi_madt_generic_translator *)header; + + pr_info("ITS: ID: 0x%x\n", its->translation_id); + its_probe(its->base_address, 2 * SZ_64K); + return 0; +} + +void __init its_acpi_probe(struct acpi_table_header *table) +{ + int count; + + count = acpi_parse_entries(ACPI_SIG_MADT, + sizeof(struct acpi_table_madt), + gic_acpi_parse_madt_its, table, + ACPI_MADT_TYPE_GENERIC_TRANSLATOR, 0); + if (!count) + pr_info("No valid GIC ITS entries exist\n"); + else if (count < 0) + pr_err("Error during GIC ITS entries parsing\n"); +} +#endif + void its_init(struct rdists *rdists, struct irq_domain *domain) { struct its_node *its; diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index d78589c..d02ca93 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -1138,6 +1138,8 @@ madt_dist: goto out_redist_unmap; }

+ its_acpi_probe(table); + err = gic_init_bases(dist_base, redist_regs, redist_regions, 0, NULL); if (err) goto out_dist_unmap; diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h index 27e77d5..a8a6ff5 100644 --- a/include/linux/irqchip/arm-gic-acpi.h +++ b/include/linux/irqchip/arm-gic-acpi.h @@ -26,6 +26,7 @@ struct acpi_table_header; int gic_v2_acpi_init(struct acpi_table_header *table); int gic_v3_acpi_init(struct acpi_table_header *table); void acpi_gic_init(void); +void its_acpi_probe(struct acpi_table_header *table); #else static inline void acpi_gic_init(void) { } #endif

From: Tomasz Nowicki tomasz.nowicki@linaro.org

MMCFG table seems to be architecture independent and it makes sense to share common code across all architectures. The ones that may need architectural specific actions have default prototype (__weak).

Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Tested-by: Hanjun Guo hanjun.guo@linaro.org Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/x86/include/asm/pci_x86.h | 29 ----- arch/x86/pci/acpi.c | 1 + arch/x86/pci/init.c | 1 + arch/x86/pci/mmconfig-shared.c | 200 +--------------------------------- arch/x86/pci/mmconfig_32.c | 1 + arch/x86/pci/mmconfig_64.c | 1 + drivers/acpi/Makefile | 1 + drivers/acpi/bus.c | 1 + drivers/acpi/mmconfig.c | 242 +++++++++++++++++++++++++++++++++++++++++ include/linux/mmconfig.h | 58 ++++++++++ include/linux/pci.h | 8 -- 11 files changed, 308 insertions(+), 235 deletions(-) create mode 100644 drivers/acpi/mmconfig.c create mode 100644 include/linux/mmconfig.h

diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h index 164e3f8..763f19a 100644 --- a/arch/x86/include/asm/pci_x86.h +++ b/arch/x86/include/asm/pci_x86.h @@ -123,35 +123,6 @@ extern int __init pcibios_init(void); extern int pci_legacy_init(void); extern void pcibios_fixup_irqs(void);

-/* pci-mmconfig.c */ - -/* "PCI MMCONFIG %04x [bus %02x-%02x]" */ -#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) - -struct pci_mmcfg_region { - struct list_head list; - struct resource res; - u64 address; - char __iomem *virt; - u16 segment; - u8 start_bus; - u8 end_bus; - char name[PCI_MMCFG_RESOURCE_NAME_LEN]; -}; - -extern int __init pci_mmcfg_arch_init(void); -extern void __init pci_mmcfg_arch_free(void); -extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg); -extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg); -extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, - phys_addr_t addr); -extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end); -extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); - -extern struct list_head pci_mmcfg_list; - -#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) - /* * AMD Fam10h CPUs are buggy, and cannot access MMIO config space * on their northbrige except through the * %eax register. As such, you MUST diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c index ff99117..1d3801f 100644 --- a/arch/x86/pci/acpi.c +++ b/arch/x86/pci/acpi.c @@ -4,6 +4,7 @@ #include <linux/irq.h> #include <linux/dmi.h> #include <linux/slab.h> +#include <linux/mmconfig.h> #include <asm/numa.h> #include <asm/pci_x86.h>

diff --git a/arch/x86/pci/init.c b/arch/x86/pci/init.c index adb62aa..b4a55df 100644 --- a/arch/x86/pci/init.c +++ b/arch/x86/pci/init.c @@ -1,5 +1,6 @@ #include <linux/pci.h> #include <linux/init.h> +#include <linux/mmconfig.h> #include <asm/pci_x86.h> #include <asm/x86_init.h>

diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 5707040..87e8b6c 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -18,6 +18,7 @@ #include <linux/slab.h> #include <linux/mutex.h> #include <linux/rculist.h> +#include <linux/mmconfig.h> #include <asm/e820.h> #include <asm/pci_x86.h> #include <asm/acpi.h> @@ -27,103 +28,6 @@ /* Indicate if the mmcfg resources have been placed into the resource table. */ static bool pci_mmcfg_running_state; static bool pci_mmcfg_arch_init_failed; -static DEFINE_MUTEX(pci_mmcfg_lock); - -LIST_HEAD(pci_mmcfg_list); - -static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) -{ - if (cfg->res.parent) - release_resource(&cfg->res); - list_del(&cfg->list); - kfree(cfg); -} - -static void __init free_all_mmcfg(void) -{ - struct pci_mmcfg_region *cfg, *tmp; - - pci_mmcfg_arch_free(); - list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list) - pci_mmconfig_remove(cfg); -} - -static void list_add_sorted(struct pci_mmcfg_region *new) -{ - struct pci_mmcfg_region *cfg; - - /* keep list sorted by segment and starting bus number */ - list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) { - if (cfg->segment > new->segment || - (cfg->segment == new->segment && - cfg->start_bus >= new->start_bus)) { - list_add_tail_rcu(&new->list, &cfg->list); - return; - } - } - list_add_tail_rcu(&new->list, &pci_mmcfg_list); -} - -static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start, - int end, u64 addr) -{ - struct pci_mmcfg_region *new; - struct resource *res; - - if (addr == 0) - return NULL; - - new = kzalloc(sizeof(*new), GFP_KERNEL); - if (!new) - return NULL; - - new->address = addr; - new->segment = segment; - new->start_bus = start; - new->end_bus = end; - - res = &new->res; - res->start = addr + PCI_MMCFG_BUS_OFFSET(start); - res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1; - res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; - snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN, - "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end); - res->name = new->name; - - return new; -} - -static struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start, - int end, u64 addr) -{ - struct pci_mmcfg_region *new; - - new = pci_mmconfig_alloc(segment, start, end, addr); - if (new) { - mutex_lock(&pci_mmcfg_lock); - list_add_sorted(new); - mutex_unlock(&pci_mmcfg_lock); - - pr_info(PREFIX - "MMCONFIG for domain %04x [bus %02x-%02x] at %pR " - "(base %#lx)\n", - segment, start, end, &new->res, (unsigned long)addr); - } - - return new; -} - -struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus) -{ - struct pci_mmcfg_region *cfg; - - list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) - if (cfg->segment == segment && - cfg->start_bus <= bus && bus <= cfg->end_bus) - return cfg; - - return NULL; -}

static const char *__init pci_mmcfg_e7520(void) { @@ -543,7 +447,7 @@ static void __init pci_mmcfg_reject_broken(int early) } }

-static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, +int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, struct acpi_mcfg_allocation *cfg) { int year; @@ -566,50 +470,6 @@ static int __init acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, return -EINVAL; }

-static int __init pci_parse_mcfg(struct acpi_table_header *header) -{ - struct acpi_table_mcfg *mcfg; - struct acpi_mcfg_allocation *cfg_table, *cfg; - unsigned long i; - int entries; - - if (!header) - return -EINVAL; - - mcfg = (struct acpi_table_mcfg *)header; - - /* how many config structures do we have */ - free_all_mmcfg(); - entries = 0; - i = header->length - sizeof(struct acpi_table_mcfg); - while (i >= sizeof(struct acpi_mcfg_allocation)) { - entries++; - i -= sizeof(struct acpi_mcfg_allocation); - } - if (entries == 0) { - pr_err(PREFIX "MMCONFIG has no entries\n"); - return -ENODEV; - } - - cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1]; - for (i = 0; i < entries; i++) { - cfg = &cfg_table[i]; - if (acpi_mcfg_check_entry(mcfg, cfg)) { - free_all_mmcfg(); - return -ENODEV; - } - - if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number, - cfg->end_bus_number, cfg->address) == NULL) { - pr_warn(PREFIX "no memory for MCFG entries\n"); - free_all_mmcfg(); - return -ENOMEM; - } - } - - return 0; -} - #ifdef CONFIG_ACPI_APEI extern int (*arch_apei_filter_addr)(int (*func)(__u64 start, __u64 size, void *data), void *data); @@ -720,39 +580,6 @@ static int __init pci_mmcfg_late_insert_resources(void) */ late_initcall(pci_mmcfg_late_insert_resources);

-static int __init pci_mmconfig_inject(struct pci_mmcfg_region *cfg) -{ - struct pci_mmcfg_region *cfg_conflict; - int err = 0; - - mutex_lock(&pci_mmcfg_lock); - cfg_conflict = pci_mmconfig_lookup(cfg->segment, cfg->start_bus); - if (cfg_conflict) { - if (cfg_conflict->end_bus < cfg->end_bus) - pr_info(FW_INFO "MMCONFIG for " - "domain %04x [bus %02x-%02x] " - "only partially covers this bridge\n", - cfg_conflict->segment, cfg_conflict->start_bus, - cfg_conflict->end_bus); - err = -EEXIST; - goto out; - } - - if (pci_mmcfg_arch_map(cfg)) { - pr_warn("fail to map MMCONFIG %pR.\n", &cfg->res); - err = -ENOMEM; - goto out; - } else { - list_add_sorted(cfg); - pr_info("MMCONFIG at %pR (base %#lx)\n", - &cfg->res, (unsigned long)cfg->address); - - } -out: - mutex_unlock(&pci_mmcfg_lock); - return err; -} - /* Add MMCFG information for host bridges */ int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, phys_addr_t addr) @@ -801,26 +628,3 @@ error: kfree(cfg); return rc; } - -/* Delete MMCFG information for host bridges */ -int pci_mmconfig_delete(u16 seg, u8 start, u8 end) -{ - struct pci_mmcfg_region *cfg; - - mutex_lock(&pci_mmcfg_lock); - list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) - if (cfg->segment == seg && cfg->start_bus == start && - cfg->end_bus == end) { - list_del_rcu(&cfg->list); - synchronize_rcu(); - pci_mmcfg_arch_unmap(cfg); - if (cfg->res.parent) - release_resource(&cfg->res); - mutex_unlock(&pci_mmcfg_lock); - kfree(cfg); - return 0; - } - mutex_unlock(&pci_mmcfg_lock); - - return -ENOENT; -} diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c index 43984bc..d774672 100644 --- a/arch/x86/pci/mmconfig_32.c +++ b/arch/x86/pci/mmconfig_32.c @@ -12,6 +12,7 @@ #include <linux/pci.h> #include <linux/init.h> #include <linux/rcupdate.h> +#include <linux/mmconfig.h> #include <asm/e820.h> #include <asm/pci_x86.h>

diff --git a/arch/x86/pci/mmconfig_64.c b/arch/x86/pci/mmconfig_64.c index bea5249..1209596 100644 --- a/arch/x86/pci/mmconfig_64.c +++ b/arch/x86/pci/mmconfig_64.c @@ -10,6 +10,7 @@ #include <linux/acpi.h> #include <linux/bitmap.h> #include <linux/rcupdate.h> +#include <linux/mmconfig.h> #include <asm/e820.h> #include <asm/pci_x86.h>

diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index 8321430..e32b8cd 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_ACPI_BUTTON) += button.o obj-$(CONFIG_ACPI_FAN) += fan.o obj-$(CONFIG_ACPI_VIDEO) += video.o obj-$(CONFIG_ACPI_PCI_SLOT) += pci_slot.o +obj-$(CONFIG_PCI_MMCONFIG) += mmconfig.o obj-$(CONFIG_ACPI_PROCESSOR) += processor.o obj-y += container.o obj-$(CONFIG_ACPI_THERMAL) += thermal.o diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 513e7230e..f9a8e5e 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -41,6 +41,7 @@ #include <acpi/apei.h> #include <linux/dmi.h> #include <linux/suspend.h> +#include <linux/mmconfig.h>

#include "internal.h"

diff --git a/drivers/acpi/mmconfig.c b/drivers/acpi/mmconfig.c new file mode 100644 index 0000000..d62dccda --- /dev/null +++ b/drivers/acpi/mmconfig.c @@ -0,0 +1,242 @@ +/* + * Arch agnostic low-level direct PCI config space access via MMCONFIG + * + * Per-architecture code takes care of the mappings, region validation and + * accesses themselves. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/mutex.h> +#include <linux/rculist.h> +#include <linux/mmconfig.h> + +#define PREFIX "PCI: " + +static DEFINE_MUTEX(pci_mmcfg_lock); + +LIST_HEAD(pci_mmcfg_list); + +static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg) +{ + if (cfg->res.parent) + release_resource(&cfg->res); + list_del(&cfg->list); + kfree(cfg); +} + +void __init free_all_mmcfg(void) +{ + struct pci_mmcfg_region *cfg, *tmp; + + pci_mmcfg_arch_free(); + list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list) + pci_mmconfig_remove(cfg); +} + +void list_add_sorted(struct pci_mmcfg_region *new) +{ + struct pci_mmcfg_region *cfg; + + /* keep list sorted by segment and starting bus number */ + list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) { + if (cfg->segment > new->segment || + (cfg->segment == new->segment && + cfg->start_bus >= new->start_bus)) { + list_add_tail_rcu(&new->list, &cfg->list); + return; + } + } + list_add_tail_rcu(&new->list, &pci_mmcfg_list); +} + +struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start, + int end, u64 addr) +{ + struct pci_mmcfg_region *new; + struct resource *res; + + if (addr == 0) + return NULL; + + new = kzalloc(sizeof(*new), GFP_KERNEL); + if (!new) + return NULL; + + new->address = addr; + new->segment = segment; + new->start_bus = start; + new->end_bus = end; + + res = &new->res; + res->start = addr + PCI_MMCFG_BUS_OFFSET(start); + res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_BUSY; + snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN, + "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end); + res->name = new->name; + + return new; +} + +struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, + int end, u64 addr) +{ + struct pci_mmcfg_region *new; + + new = pci_mmconfig_alloc(segment, start, end, addr); + if (new) { + mutex_lock(&pci_mmcfg_lock); + list_add_sorted(new); + mutex_unlock(&pci_mmcfg_lock); + + pr_info(PREFIX + "MMCONFIG for domain %04x [bus %02x-%02x] at %pR " + "(base %#lx)\n", + segment, start, end, &new->res, (unsigned long)addr); + } + + return new; +} + +int __init pci_mmconfig_inject(struct pci_mmcfg_region *cfg) +{ + struct pci_mmcfg_region *cfg_conflict; + int err = 0; + + mutex_lock(&pci_mmcfg_lock); + cfg_conflict = pci_mmconfig_lookup(cfg->segment, cfg->start_bus); + if (cfg_conflict) { + if (cfg_conflict->end_bus < cfg->end_bus) + pr_info(FW_INFO "MMCONFIG for " + "domain %04x [bus %02x-%02x] " + "only partially covers this bridge\n", + cfg_conflict->segment, cfg_conflict->start_bus, + cfg_conflict->end_bus); + err = -EEXIST; + goto out; + } + + if (pci_mmcfg_arch_map(cfg)) { + pr_warn("fail to map MMCONFIG %pR.\n", &cfg->res); + err = -ENOMEM; + goto out; + } else { + list_add_sorted(cfg); + pr_info("MMCONFIG at %pR (base %#lx)\n", + &cfg->res, (unsigned long)cfg->address); + + } +out: + mutex_unlock(&pci_mmcfg_lock); + return err; +} + +struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus) +{ + struct pci_mmcfg_region *cfg; + + list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) + if (cfg->segment == segment && + cfg->start_bus <= bus && bus <= cfg->end_bus) + return cfg; + + return NULL; +} + +int __init __weak acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, + struct acpi_mcfg_allocation *cfg) +{ + return 0; +} + +int __init pci_parse_mcfg(struct acpi_table_header *header) +{ + struct acpi_table_mcfg *mcfg; + struct acpi_mcfg_allocation *cfg_table, *cfg; + unsigned long i; + int entries; + + if (!header) + return -EINVAL; + + mcfg = (struct acpi_table_mcfg *)header; + + /* how many config structures do we have */ + free_all_mmcfg(); + entries = 0; + i = header->length - sizeof(struct acpi_table_mcfg); + while (i >= sizeof(struct acpi_mcfg_allocation)) { + entries++; + i -= sizeof(struct acpi_mcfg_allocation); + } + if (entries == 0) { + pr_err(PREFIX "MMCONFIG has no entries\n"); + return -ENODEV; + } + + cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1]; + for (i = 0; i < entries; i++) { + cfg = &cfg_table[i]; + if (acpi_mcfg_check_entry(mcfg, cfg)) { + free_all_mmcfg(); + return -ENODEV; + } + + if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number, + cfg->end_bus_number, cfg->address) == NULL) { + pr_warn(PREFIX "no memory for MCFG entries\n"); + free_all_mmcfg(); + return -ENOMEM; + } + } + + return 0; +} + +/* Delete MMCFG information for host bridges */ +int pci_mmconfig_delete(u16 seg, u8 start, u8 end) +{ + struct pci_mmcfg_region *cfg; + + mutex_lock(&pci_mmcfg_lock); + list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) + if (cfg->segment == seg && cfg->start_bus == start && + cfg->end_bus == end) { + list_del_rcu(&cfg->list); + synchronize_rcu(); + pci_mmcfg_arch_unmap(cfg); + if (cfg->res.parent) + release_resource(&cfg->res); + mutex_unlock(&pci_mmcfg_lock); + kfree(cfg); + return 0; + } + mutex_unlock(&pci_mmcfg_lock); + + return -ENOENT; +} + +void __init __weak pci_mmcfg_early_init(void) +{ + +} + +void __init __weak pci_mmcfg_late_init(void) +{ + struct pci_mmcfg_region *cfg; + + acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg); + + if (list_empty(&pci_mmcfg_list)) + return; + + if (!pci_mmcfg_arch_init()) + free_all_mmcfg(); + + list_for_each_entry(cfg, &pci_mmcfg_list, list) + insert_resource(&iomem_resource, &cfg->res); +} diff --git a/include/linux/mmconfig.h b/include/linux/mmconfig.h new file mode 100644 index 0000000..6ccd1ee --- /dev/null +++ b/include/linux/mmconfig.h @@ -0,0 +1,58 @@ +#ifndef __MMCONFIG_H +#define __MMCONFIG_H +#ifdef __KERNEL__ + +#include <linux/types.h> +#include <linux/acpi.h> + +#ifdef CONFIG_PCI_MMCONFIG +/* "PCI MMCONFIG %04x [bus %02x-%02x]" */ +#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2) + +struct pci_mmcfg_region { + struct list_head list; + struct resource res; + u64 address; + char __iomem *virt; + u16 segment; + u8 start_bus; + u8 end_bus; + char name[PCI_MMCFG_RESOURCE_NAME_LEN]; +}; + +void pci_mmcfg_early_init(void); +void pci_mmcfg_late_init(void); +struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus); + +int pci_parse_mcfg(struct acpi_table_header *header); +struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start, + int end, u64 addr); +int pci_mmconfig_inject(struct pci_mmcfg_region *cfg); +struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start, + int end, u64 addr); +void list_add_sorted(struct pci_mmcfg_region *new); +int acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, + struct acpi_mcfg_allocation *cfg); +void free_all_mmcfg(void); +int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end, + phys_addr_t addr); +int pci_mmconfig_delete(u16 seg, u8 start, u8 end); + +/* Arch specific calls */ +int pci_mmcfg_arch_init(void); +void pci_mmcfg_arch_free(void); +int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg); +void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg); + +extern struct list_head pci_mmcfg_list; + +#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20) +#else /* CONFIG_PCI_MMCONFIG */ +static inline void pci_mmcfg_late_init(void) { } +static inline void pci_mmcfg_early_init(void) { } +static inline void *pci_mmconfig_lookup(int segment, int bus) +{ return NULL; } +#endif /* CONFIG_PCI_MMCONFIG */ + +#endif /* __KERNEL__ */ +#endif /* __MMCONFIG_H */ diff --git a/include/linux/pci.h b/include/linux/pci.h index 1f1ce73..7474225 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1651,14 +1651,6 @@ void pcibios_penalize_isa_irq(int irq, int active); extern struct dev_pm_ops pcibios_pm_ops; #endif

-#ifdef CONFIG_PCI_MMCONFIG -void __init pci_mmcfg_early_init(void); -void __init pci_mmcfg_late_init(void); -#else -static inline void pci_mmcfg_early_init(void) { } -static inline void pci_mmcfg_late_init(void) { } -#endif - int pci_ext_cfg_avail(void);

void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);

From: Tomasz Nowicki tomasz.nowicki@linaro.org

mmconfig_64.c version is going to be default implementation for arch agnostic low-level direct PCI config space accessors via MMCONFIG. However, now it initialize raw_pci_ext_ops pointer which is used in x86 specific code only. Moreover, mmconfig_32.c is doing the same thing at the same time.

Move it to mmconfig_shared.c so it becomes common for both and mmconfig_64.c turns out to be purely arch agnostic.

Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Tested-by: Hanjun Guo hanjun.guo@linaro.org Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/x86/pci/mmconfig-shared.c | 10 ++++++++-- arch/x86/pci/mmconfig_32.c | 10 ++-------- arch/x86/pci/mmconfig_64.c | 6 ++---- include/linux/mmconfig.h | 4 ++++ 4 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c index 87e8b6c..5acb006 100644 --- a/arch/x86/pci/mmconfig-shared.c +++ b/arch/x86/pci/mmconfig-shared.c @@ -29,6 +29,11 @@ static bool pci_mmcfg_running_state; static bool pci_mmcfg_arch_init_failed;

+const struct pci_raw_ops pci_mmcfg = { + .read = pci_mmcfg_read, + .write = pci_mmcfg_write, +}; + static const char *__init pci_mmcfg_e7520(void) { u32 win; @@ -512,9 +517,10 @@ static void __init __pci_mmcfg_init(int early) } }

- if (pci_mmcfg_arch_init()) + if (pci_mmcfg_arch_init()) { + raw_pci_ext_ops = &pci_mmcfg; pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF; - else { + } else { free_all_mmcfg(); pci_mmcfg_arch_init_failed = true; } diff --git a/arch/x86/pci/mmconfig_32.c b/arch/x86/pci/mmconfig_32.c index d774672..c0106a6 100644 --- a/arch/x86/pci/mmconfig_32.c +++ b/arch/x86/pci/mmconfig_32.c @@ -50,7 +50,7 @@ static void pci_exp_set_dev_base(unsigned int base, int bus, int devfn) } }

-static int pci_mmcfg_read(unsigned int seg, unsigned int bus, +int pci_mmcfg_read(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value) { unsigned long flags; @@ -89,7 +89,7 @@ err: *value = -1; return 0; }

-static int pci_mmcfg_write(unsigned int seg, unsigned int bus, +int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value) { unsigned long flags; @@ -126,15 +126,9 @@ static int pci_mmcfg_write(unsigned int seg, unsigned int bus, return 0; }

-const struct pci_raw_ops pci_mmcfg = { - .read = pci_mmcfg_read, - .write = pci_mmcfg_write, -}; - int __init pci_mmcfg_arch_init(void) { printk(KERN_INFO "PCI: Using MMCONFIG for extended config space\n"); - raw_pci_ext_ops = &pci_mmcfg; return 1; }

diff --git a/arch/x86/pci/mmconfig_64.c b/arch/x86/pci/mmconfig_64.c index 1209596..ff2c50c 100644 --- a/arch/x86/pci/mmconfig_64.c +++ b/arch/x86/pci/mmconfig_64.c @@ -25,7 +25,7 @@ static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned i return NULL; }

-static int pci_mmcfg_read(unsigned int seg, unsigned int bus, +int pci_mmcfg_read(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value) { char __iomem *addr; @@ -59,7 +59,7 @@ err: *value = -1; return 0; }

-static int pci_mmcfg_write(unsigned int seg, unsigned int bus, +int pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value) { char __iomem *addr; @@ -121,8 +121,6 @@ int __init pci_mmcfg_arch_init(void) return 0; }

- raw_pci_ext_ops = &pci_mmcfg; - return 1; }

diff --git a/include/linux/mmconfig.h b/include/linux/mmconfig.h index 6ccd1ee..ae8ec83 100644 --- a/include/linux/mmconfig.h +++ b/include/linux/mmconfig.h @@ -43,6 +43,10 @@ int pci_mmcfg_arch_init(void); void pci_mmcfg_arch_free(void); int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg); void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg); +int pci_mmcfg_read(unsigned int seg, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *value); +int pci_mmcfg_write(unsigned int seg, unsigned int bus, + unsigned int devfn, int reg, int len, u32 value);

extern struct list_head pci_mmcfg_list;

From: Tomasz Nowicki tomasz.nowicki@linaro.org

MMCFG can be used perfectly for all architectures which support ACPI. ACPI mandates MMCFG to describe PCI config space ranges which means we should use MMCONFIG accessors by default.

Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Tested-by: Hanjun Guo hanjun.guo@linaro.org Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/acpi/mmconfig.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)

diff --git a/drivers/acpi/mmconfig.c b/drivers/acpi/mmconfig.c index c0ad05f..c9c6e05 100644 --- a/drivers/acpi/mmconfig.c +++ b/drivers/acpi/mmconfig.c @@ -23,6 +23,26 @@ static DEFINE_MUTEX(pci_mmcfg_lock);

LIST_HEAD(pci_mmcfg_list);

+/* + * raw_pci_read/write - ACPI PCI config space accessors. + * + * ACPI spec defines MMCFG as the way we can access PCI config space, + * so let MMCFG be default (__weak). + * + * If platform needs more fancy stuff, should provides its own implementation. + */ +int __weak raw_pci_read(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *val) +{ + return pci_mmcfg_read(domain, bus, devfn, reg, len, val); +} + +int __weak raw_pci_write(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 val) +{ + return pci_mmcfg_write(domain, bus, devfn, reg, len, val); +} + static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn) {

From: Tomasz Nowicki tomasz.nowicki@linaro.org

Host driver is made in old fashion, it should be revisited once new way of root bus creation get upstream.

Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/include/asm/pci.h | 8 + arch/arm64/kernel/Makefile | 1 + arch/arm64/kernel/pci-acpi.c | 348 +++++++++++++++++++++++++++++++++++++++++++ arch/arm64/kernel/pci.c | 24 --- drivers/pci/pci.c | 90 ++++++----- 5 files changed, 406 insertions(+), 65 deletions(-) create mode 100644 arch/arm64/kernel/pci-acpi.c

diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h index 4e47457..76275e1 100644 --- a/arch/arm64/include/asm/pci.h +++ b/arch/arm64/include/asm/pci.h @@ -29,6 +29,14 @@ extern int isa_dma_bridge_buggy; #ifdef CONFIG_PCI

#ifdef CONFIG_ACPI +struct pci_controller { + struct acpi_device *companion; + int segment; + int node; /* nearest node with memory or NUMA_NO_NODE for global allocation */ +}; + +#define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata) + /* * ARM64 PCI config space access primitives. */ diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile index 426d076..9add37b 100644 --- a/arch/arm64/kernel/Makefile +++ b/arch/arm64/kernel/Makefile @@ -35,6 +35,7 @@ arm64-obj-$(CONFIG_KGDB) += kgdb.o arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o arm64-obj-$(CONFIG_PCI) += pci.o arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o +arm64-obj-$(CONFIG_ACPI) += pci-acpi.o arm64-obj-$(CONFIG_ACPI) += acpi.o

obj-y += $(arm64-obj-y) vdso/ diff --git a/arch/arm64/kernel/pci-acpi.c b/arch/arm64/kernel/pci-acpi.c new file mode 100644 index 0000000..1826b10 --- /dev/null +++ b/arch/arm64/kernel/pci-acpi.c @@ -0,0 +1,348 @@ +/* + * Code borrowed from powerpc/kernel/pci-common.c and arch/ia64/pci/pci.c + * + * Copyright (c) 2002, 2005 Hewlett-Packard Development Company, L.P. + * David Mosberger-Tang davidm@hpl.hp.com + * Bjorn Helgaas bjorn.helgaas@hp.com + * Copyright (C) 2004 Silicon Graphics, Inc. + * Copyright (C) 2003 Anton Blanchard anton@au.ibm.com, IBM + * Copyright (C) 2014 ARM Ltd. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + */ + +#include <linux/acpi.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mm.h> +#include <linux/mmconfig.h> +#include <linux/of_address.h> +#include <linux/of_pci.h> +#include <linux/of_platform.h> +#include <linux/pci.h> +#include <linux/pci-acpi.h> +#include <linux/slab.h> + +#include <asm/pci-bridge.h> + +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) +{ + ACPI_COMPANION_SET(&bridge->dev, + PCI_CONTROLLER(bridge->bus)->companion); + + return 0; +} + +void pcibios_add_bus(struct pci_bus *bus) +{ + acpi_pci_add_bus(bus); +} + +void pcibios_remove_bus(struct pci_bus *bus) +{ + acpi_pci_remove_bus(bus); +} + +int +pcibios_enable_device (struct pci_dev *dev, int mask) +{ + int ret; + + ret = pci_enable_resources(dev, mask); + if (ret < 0) + return ret; + + if (!dev->msi_enabled) + return acpi_pci_irq_enable(dev); + return 0; +} + +void +pcibios_disable_device (struct pci_dev *dev) +{ + BUG_ON(atomic_read(&dev->enable_cnt)); + if (!dev->msi_enabled) + acpi_pci_irq_disable(dev); +} + +static int pci_read(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *value) +{ + return raw_pci_read(pci_domain_nr(bus), bus->number, + devfn, where, size, value); +} + +static int pci_write(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 value) +{ + return raw_pci_write(pci_domain_nr(bus), bus->number, + devfn, where, size, value); +} + +struct pci_ops pci_root_ops = { + .read = pci_read, + .write = pci_write, +}; + +static struct pci_controller *alloc_pci_controller(int seg) +{ + struct pci_controller *controller; + + controller = kzalloc(sizeof(*controller), GFP_KERNEL); + if (!controller) + return NULL; + + controller->segment = seg; + return controller; +} + +struct pci_root_info { + struct acpi_device *bridge; + struct pci_controller *controller; + struct list_head resources; + struct resource *res; + unsigned int res_num; + char *name; +}; + +static acpi_status resource_to_window(struct acpi_resource *resource, + struct acpi_resource_address64 *addr) +{ + acpi_status status; + + /* + * We're only interested in _CRS descriptors that are + * - address space descriptors for memory + * - non-zero size + * - producers, i.e., the address space is routed downstream, + * not consumed by the bridge itself + */ + status = acpi_resource_to_address64(resource, addr); + if (ACPI_SUCCESS(status) && + (addr->resource_type == ACPI_MEMORY_RANGE || + addr->resource_type == ACPI_IO_RANGE) && + addr->address.address_length && + addr->producer_consumer == ACPI_PRODUCER) + return AE_OK; + + return AE_ERROR; +} + +static acpi_status count_window(struct acpi_resource *resource, void *data) +{ + unsigned int *windows = (unsigned int *) data; + struct acpi_resource_address64 addr; + acpi_status status; + + status = resource_to_window(resource, &addr); + if (ACPI_SUCCESS(status)) + (*windows)++; + + return AE_OK; +} + +static acpi_status add_window(struct acpi_resource *res, void *data) +{ + struct pci_root_info *info = data; + struct resource *resource; + struct acpi_resource_address64 addr; + resource_size_t offset; + acpi_status status; + unsigned long flags; + struct resource *root; + u64 start; + + /* Return AE_OK for non-window resources to keep scanning for more */ + status = resource_to_window(res, &addr); + if (!ACPI_SUCCESS(status)) + return AE_OK; + + if (addr.resource_type == ACPI_MEMORY_RANGE) { + flags = IORESOURCE_MEM; + root = &iomem_resource; + } else if (addr.resource_type == ACPI_IO_RANGE) { + flags = IORESOURCE_IO; + root = &ioport_resource; + } else + return AE_OK; + + start = addr.address.minimum + addr.address.translation_offset; + + resource = &info->res[info->res_num]; + resource->name = info->name; + resource->flags = flags; + resource->start = start; + resource->end = resource->start + addr.address.address_length - 1; + + if (flags & IORESOURCE_IO) { + unsigned long port; + int err; + + err = pci_register_io_range(start, addr.address.address_length); + if (err) + return AE_OK; + + port = pci_address_to_pio(start); + if (port == (unsigned long)-1) + return AE_OK; + + resource->start = port; + resource->end = port + addr.address.address_length - 1; + + if (pci_remap_iospace(resource, start) < 0) + return AE_OK; + + offset = 0; + } else + offset = addr.address.translation_offset; + + if (insert_resource(root, resource)) { + dev_err(&info->bridge->dev, + "can't allocate host bridge window %pR\n", + resource); + } else { + if (addr.address.translation_offset) + dev_info(&info->bridge->dev, "host bridge window %pR " + "(PCI address [%#llx-%#llx])\n", + resource, + resource->start - addr.address.translation_offset, + resource->end - addr.address.translation_offset); + else + dev_info(&info->bridge->dev, + "host bridge window %pR\n", resource); + } + + pci_add_resource_offset(&info->resources, resource, offset); + info->res_num++; + return AE_OK; +} + +static void free_pci_root_info_res(struct pci_root_info *info) +{ + kfree(info->name); + kfree(info->res); + info->res = NULL; + info->res_num = 0; + kfree(info->controller); + info->controller = NULL; +} + +static void __release_pci_root_info(struct pci_root_info *info) +{ + int i; + struct resource *res; + + for (i = 0; i < info->res_num; i++) { + res = &info->res[i]; + + if (!res->parent) + continue; + + if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + continue; + + release_resource(res); + } + + free_pci_root_info_res(info); + kfree(info); +} + +static void release_pci_root_info(struct pci_host_bridge *bridge) +{ + struct pci_root_info *info = bridge->release_data; + + __release_pci_root_info(info); +} + +static int +probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device, + int busnum, int domain) +{ + char *name; + + name = kmalloc(16, GFP_KERNEL); + if (!name) + return -ENOMEM; + + sprintf(name, "PCI Bus %04x:%02x", domain, busnum); + info->bridge = device; + info->name = name; + + acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, + &info->res_num); + if (info->res_num) { + info->res = + kzalloc_node(sizeof(*info->res) * info->res_num, + GFP_KERNEL, info->controller->node); + if (!info->res) { + kfree(name); + return -ENOMEM; + } + + info->res_num = 0; + acpi_walk_resources(device->handle, METHOD_NAME__CRS, + add_window, info); + } else + kfree(name); + + return 0; +} + +/* Root bridge scanning */ +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + struct acpi_device *device = root->device; + int domain = root->segment; + int bus = root->secondary.start; + struct pci_controller *controller; + struct pci_root_info *info = NULL; + int busnum = root->secondary.start; + struct pci_bus *pbus; + int ret; + + controller = alloc_pci_controller(domain); + if (!controller) + return NULL; + + controller->companion = device; + controller->node = acpi_get_node(device->handle); + + info = kzalloc(sizeof(*info), GFP_KERNEL); + if (!info) { + dev_err(&device->dev, + "pci_bus %04x:%02x: ignored (out of memory)\n", + domain, busnum); + kfree(controller); + return NULL; + } + + info->controller = controller; + INIT_LIST_HEAD(&info->resources); + + ret = probe_pci_root_info(info, device, busnum, domain); + if (ret) { + kfree(info->controller); + kfree(info); + return NULL; + } + /* insert busn resource at first */ + pci_add_resource(&info->resources, &root->secondary); + + pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller, + &info->resources); + if (!pbus) { + pci_free_resource_list(&info->resources); + __release_pci_root_info(info); + return NULL; + } + + pci_set_host_bridge_release(to_pci_host_bridge(pbus->bridge), + release_pci_root_info, info); + pci_scan_child_bus(pbus); + return pbus; +} diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index 3356023..7642075 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -57,27 +57,3 @@ int pcibios_add_device(struct pci_dev *dev)

return 0; } - -/* - * raw_pci_read/write - Platform-specific PCI config space access. - */ -int raw_pci_read(unsigned int domain, unsigned int bus, - unsigned int devfn, int reg, int len, u32 *val) -{ - return -ENXIO; -} - -int raw_pci_write(unsigned int domain, unsigned int bus, - unsigned int devfn, int reg, int len, u32 val) -{ - return -ENXIO; -} - -#ifdef CONFIG_ACPI -/* Root bridge scanning */ -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - /* TODO: Should be revisited when implementing PCI on ACPI */ - return NULL; -} -#endif diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 0008c95..0eec993 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4486,47 +4486,55 @@ int pci_get_new_domain_nr(void) #ifdef CONFIG_PCI_DOMAINS_GENERIC void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent) { - static int use_dt_domains = -1; - int domain = of_get_pci_domain_nr(parent->of_node); - - /* - * Check DT domain and use_dt_domains values. - * - * If DT domain property is valid (domain >= 0) and - * use_dt_domains != 0, the DT assignment is valid since this means - * we have not previously allocated a domain number by using - * pci_get_new_domain_nr(); we should also update use_dt_domains to - * 1, to indicate that we have just assigned a domain number from - * DT. - * - * If DT domain property value is not valid (ie domain < 0), and we - * have not previously assigned a domain number from DT - * (use_dt_domains != 1) we should assign a domain number by - * using the: - * - * pci_get_new_domain_nr() - * - * API and update the use_dt_domains value to keep track of method we - * are using to assign domain numbers (use_dt_domains = 0). - * - * All other combinations imply we have a platform that is trying - * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), - * which is a recipe for domain mishandling and it is prevented by - * invalidating the domain value (domain = -1) and printing a - * corresponding error. - */ - if (domain >= 0 && use_dt_domains) { - use_dt_domains = 1; - } else if (domain < 0 && use_dt_domains != 1) { - use_dt_domains = 0; - domain = pci_get_new_domain_nr(); - } else { - dev_err(parent, "Node %s has inconsistent "linux,pci-domain" property in DT\n", - parent->of_node->full_name); - domain = -1; - } - - bus->domain_nr = domain; + static int use_dt_domains = -1; + int domain; + + if (!acpi_disabled) { + domain = PCI_CONTROLLER(bus)->segment; + goto out; + } + + domain = of_get_pci_domain_nr(parent->of_node); + + + /* + * Check DT domain and use_dt_domains values. + * + * If DT domain property is valid (domain >= 0) and + * use_dt_domains != 0, the DT assignment is valid since this means + * we have not previously allocated a domain number by using + * pci_get_new_domain_nr(); we should also update use_dt_domains to + * 1, to indicate that we have just assigned a domain number from + * DT. + * + * If DT domain property value is not valid (ie domain < 0), and we + * have not previously assigned a domain number from DT + * (use_dt_domains != 1) we should assign a domain number by + * using the: + * + * pci_get_new_domain_nr() + * + * API and update the use_dt_domains value to keep track of method we + * are using to assign domain numbers (use_dt_domains = 0). + * + * All other combinations imply we have a platform that is trying + * to mix domain numbers obtained from DT and pci_get_new_domain_nr(), + * which is a recipe for domain mishandling and it is prevented by + * invalidating the domain value (domain = -1) and printing a + * corresponding error. + */ + if (domain >= 0 && use_dt_domains) { + use_dt_domains = 1; + } else if (domain < 0 && use_dt_domains != 1) { + use_dt_domains = 0; + domain = pci_get_new_domain_nr(); + } else { + dev_err(parent, "Node %s has inconsistent "linux,pci-domain" property in DT\n", + parent->of_node->full_name); + domain = -1; + } +out: + bus->domain_nr = domain; } #endif #endif

From: Tomasz Nowicki tomasz.nowicki@linaro.org

Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/net/phy/mdio-octeon.c | 62 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-)

diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c index 428ae75..3ceb90b 100644 --- a/drivers/net/phy/mdio-octeon.c +++ b/drivers/net/phy/mdio-octeon.c @@ -14,6 +14,7 @@ #include <linux/gfp.h> #include <linux/phy.h> #include <linux/io.h> +#include <linux/acpi.h>

#ifdef CONFIG_CAVIUM_OCTEON_SOC #include <asm/octeon/octeon.h> @@ -265,6 +266,62 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id, return 0; }

+#ifdef CONFIG_ACPI +static acpi_status +acpi_register_phy(acpi_handle handle, u32 lvl, void *context, void **rv) +{ + struct mii_bus *mdio = context; + struct acpi_device *adev; + struct phy_device *phy; + u32 phy_id; + + if (acpi_bus_get_device(handle, &adev)) + return AE_OK; + + if (acpi_dev_prop_read_single(adev, "phy-channel", DEV_PROP_U32, + &phy_id)) + return AE_OK; + + phy = get_phy_device(mdio, phy_id, false); + if (!phy || IS_ERR(phy)) + return AE_OK; + + if (phy_device_register(phy)) + phy_device_free(phy); + + return AE_OK; +} + +static int +acpi_mdiobus_register(struct mii_bus *mdio) +{ + int i, ret; + + /* Mask out all PHYs from auto probing. */ + mdio->phy_mask = ~0; + + /* Clear all the IRQ properties */ + if (mdio->irq) + for (i = 0; i < PHY_MAX_ADDR; i++) + mdio->irq[i] = PHY_POLL; + + /* Register the MDIO bus */ + ret = mdiobus_register(mdio); + if (ret) + return ret; + + acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_HANDLE(mdio->parent), 1, + acpi_register_phy, NULL, mdio, NULL); + return 0; +} +#else +static int +acpi_mdiobus_register(struct mii_bus *mdio) +{ + return 0; +} +#endif + static int octeon_mdiobus_probe(struct platform_device *pdev) { struct octeon_mdiobus *bus; @@ -317,7 +374,10 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)

platform_set_drvdata(pdev, bus);

- err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node); + if (pdev->dev.of_node) + err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node); + else + err = acpi_mdiobus_register(bus->mii_bus); if (err) goto fail_register;

From: Tomasz Nowicki tomasz.nowicki@linaro.org

Some MCFG tables may be broken or the underlying hardware may not be fully compliant with the PCIe ECAM mechanism. This patch provides a mechanism to override the default mmconfig read/write routines and/or do other MCFG related fixups.

Signed-off-by: Mark Salter msalter@redhat.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/kernel/pci-acpi.c | 12 +++++ drivers/acpi/mmconfig.c | 103 ++++++++++++++++++++++++++------------ include/asm-generic/vmlinux.lds.h | 7 +++ include/linux/mmconfig.h | 24 +++++++++ 4 files changed, 115 insertions(+), 31 deletions(-)

diff --git a/arch/arm64/kernel/pci-acpi.c b/arch/arm64/kernel/pci-acpi.c index 1826b10..517d570 100644 --- a/arch/arm64/kernel/pci-acpi.c +++ b/arch/arm64/kernel/pci-acpi.c @@ -297,6 +297,7 @@ probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device, struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) { struct acpi_device *device = root->device; + struct pci_mmcfg_region *mcfg; int domain = root->segment; int bus = root->secondary.start; struct pci_controller *controller; @@ -305,6 +306,17 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) struct pci_bus *pbus; int ret;

+ /* we need mmconfig */ + mcfg = pci_mmconfig_lookup(domain, busnum); + if (!mcfg) { + pr_err("pci_bus %04x:%02x has no MCFG table\n", + domain, busnum); + return NULL; + } + + if (mcfg->fixup) + (*mcfg->fixup)(root, mcfg); + controller = alloc_pci_controller(domain); if (!controller) return NULL; diff --git a/drivers/acpi/mmconfig.c b/drivers/acpi/mmconfig.c index c9c6e05..9c6efa5 100644 --- a/drivers/acpi/mmconfig.c +++ b/drivers/acpi/mmconfig.c @@ -43,20 +43,36 @@ int __weak raw_pci_write(unsigned int domain, unsigned int bus, return pci_mmcfg_write(domain, bus, devfn, reg, len, val); }

-static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, - unsigned int devfn) +static inline char __iomem *pci_dev_base(struct pci_mmcfg_region *cfg, + unsigned int bus, unsigned int devfn) { - struct pci_mmcfg_region *cfg = pci_mmconfig_lookup(seg, bus); + return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12)); +}

- if (cfg && cfg->virt) - return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12)); - return NULL; +static int __pci_mmcfg_read(struct pci_mmcfg_region *cfg, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *value) +{ + char __iomem *addr = pci_dev_base(cfg, bus, devfn); + + switch (len) { + case 1: + *value = mmio_config_readb(addr + reg); + break; + case 2: + *value = mmio_config_readw(addr + reg); + break; + case 4: + *value = mmio_config_readl(addr + reg); + break; + } + return 0; }

int __weak pci_mmcfg_read(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value) { - char __iomem *addr; + struct pci_mmcfg_region *cfg; + int ret;

/* Why do we have this when nobody checks it. How about a BUG()!? -AK */ if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) { @@ -65,58 +81,66 @@ err: *value = -1; }

rcu_read_lock(); - addr = pci_dev_base(seg, bus, devfn); - if (!addr) { + cfg = pci_mmconfig_lookup(seg, bus); + if (!cfg || !cfg->virt) { rcu_read_unlock(); goto err; }

+ if (cfg->read) + ret = (*cfg->read)(cfg, bus, devfn, reg, len, value); + else + ret = __pci_mmcfg_read(cfg, bus, devfn, reg, len, value); + + rcu_read_unlock(); + + return ret; +} + +static int __pci_mmcfg_write(struct pci_mmcfg_region *cfg, unsigned int bus, + unsigned int devfn, int reg, int len, u32 value) +{ + char __iomem *addr = pci_dev_base(cfg, bus, devfn); + switch (len) { case 1: - *value = mmio_config_readb(addr + reg); + mmio_config_writeb(addr + reg, value); break; case 2: - *value = mmio_config_readw(addr + reg); + mmio_config_writew(addr + reg, value); break; case 4: - *value = mmio_config_readl(addr + reg); + mmio_config_writel(addr + reg, value); break; } - rcu_read_unlock(); - return 0; }

int __weak pci_mmcfg_write(unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value) { - char __iomem *addr; + struct pci_mmcfg_region *cfg; + int ret;

/* Why do we have this when nobody checks it. How about a BUG()!? -AK */ if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) return -EINVAL;

rcu_read_lock(); - addr = pci_dev_base(seg, bus, devfn); - if (!addr) { + cfg = pci_mmconfig_lookup(seg, bus); + if (!cfg || !cfg->virt) { rcu_read_unlock(); return -EINVAL; }

- switch (len) { - case 1: - mmio_config_writeb(addr + reg, value); - break; - case 2: - mmio_config_writew(addr + reg, value); - break; - case 4: - mmio_config_writel(addr + reg, value); - break; - } + if (cfg->write) + ret = (*cfg->write)(cfg, bus, devfn, reg, len, value); + else + ret = __pci_mmcfg_write(cfg, bus, devfn, reg, len, value); + rcu_read_unlock();

- return 0; + return ret; }

static void __iomem *mcfg_ioremap(struct pci_mmcfg_region *cfg) @@ -307,10 +331,15 @@ int __init __weak acpi_mcfg_check_entry(struct acpi_table_mcfg *mcfg, return 0; }

+extern struct acpi_mcfg_fixup __start_acpi_mcfg_fixups[]; +extern struct acpi_mcfg_fixup __end_acpi_mcfg_fixups[]; + int __init pci_parse_mcfg(struct acpi_table_header *header) { struct acpi_table_mcfg *mcfg; struct acpi_mcfg_allocation *cfg_table, *cfg; + struct acpi_mcfg_fixup *fixup; + struct pci_mmcfg_region *new; unsigned long i; int entries;

@@ -332,6 +361,15 @@ int __init pci_parse_mcfg(struct acpi_table_header *header) return -ENODEV; }

+ fixup = __start_acpi_mcfg_fixups; + while (fixup < __end_acpi_mcfg_fixups) { + if (!strncmp(fixup->oem_id, header->oem_id, 6) && + !strncmp(fixup->oem_table_id, header->oem_table_id, 8)) + break; + ++fixup; + } + + cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1]; for (i = 0; i < entries; i++) { cfg = &cfg_table[i]; @@ -340,12 +378,15 @@ int __init pci_parse_mcfg(struct acpi_table_header *header) return -ENODEV; }

- if (pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number, - cfg->end_bus_number, cfg->address) == NULL) { + new = pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number, + cfg->end_bus_number, cfg->address); + if (!new) { pr_warn(PREFIX "no memory for MCFG entries\n"); free_all_mmcfg(); return -ENOMEM; } + if (fixup < __end_acpi_mcfg_fixups) + new->fixup = fixup->hook; }

return 0; diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h index 8bd374d..dd58f47 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -288,6 +288,13 @@ VMLINUX_SYMBOL(__end_pci_fixups_suspend_late) = .; \ } \ \ + /* ACPI quirks */ \ + .acpi_fixup : AT(ADDR(.acpi_fixup) - LOAD_OFFSET) { \ + VMLINUX_SYMBOL(__start_acpi_mcfg_fixups) = .; \ + *(.acpi_fixup_mcfg) \ + VMLINUX_SYMBOL(__end_acpi_mcfg_fixups) = .; \ + } \ + \ /* Built-in firmware blobs */ \ .builtin_fw : AT(ADDR(.builtin_fw) - LOAD_OFFSET) { \ VMLINUX_SYMBOL(__start_builtin_fw) = .; \ diff --git a/include/linux/mmconfig.h b/include/linux/mmconfig.h index ae8ec83..4360e9a 100644 --- a/include/linux/mmconfig.h +++ b/include/linux/mmconfig.h @@ -9,9 +9,21 @@ /* "PCI MMCONFIG %04x [bus %02x-%02x]" */ #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)

+struct acpi_pci_root; +struct pci_mmcfg_region; + +typedef int (*acpi_mcfg_fixup_t)(struct acpi_pci_root *root, + struct pci_mmcfg_region *cfg); + struct pci_mmcfg_region { struct list_head list; struct resource res; + int (*read)(struct pci_mmcfg_region *cfg, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *value); + int (*write)(struct pci_mmcfg_region *cfg, unsigned int bus, + unsigned int devfn, int reg, int len, u32 value); + acpi_mcfg_fixup_t fixup; + void *data; u64 address; char __iomem *virt; u16 segment; @@ -20,6 +32,18 @@ struct pci_mmcfg_region { char name[PCI_MMCFG_RESOURCE_NAME_LEN]; };

+struct acpi_mcfg_fixup { + char oem_id[7]; + char oem_table_id[9]; + acpi_mcfg_fixup_t hook; +}; + +/* Designate a routine to fix up buggy MCFG */ +#define DECLARE_ACPI_MCFG_FIXUP(oem_id, table_id, hook) \ + static const struct acpi_mcfg_fixup __acpi_fixup_##hook __used \ + __attribute__((__section__(".acpi_fixup_mcfg"), aligned((sizeof(void *))))) \ + = { {oem_id}, {table_id}, hook }; + void pci_mmcfg_early_init(void); void pci_mmcfg_late_init(void); struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);

From: Tomasz Nowicki tomasz.nowicki@linaro.org

With ACPI enabled, kvm_timer_hyp_init can't access any device tree information. Although registration of the virtual timer interrupt already happened when architected timers were initialized, we need to point KVM to the interrupt line used.

Signed-off-by: Alexander Spyridakis a.spyridakis@virtualopensystems.com Signed-off-by: Tomasz Nowicki tomasz.nowicki@linaro.org Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- virt/kvm/arm/arch_timer.c | 76 +++++++++++++++++++++++++++++++++++++---------- 1 file changed, 60 insertions(+), 16 deletions(-)

diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c index 98c95f2..a26c8b8 100644 --- a/virt/kvm/arm/arch_timer.c +++ b/virt/kvm/arm/arch_timer.c @@ -21,6 +21,7 @@ #include <linux/kvm.h> #include <linux/kvm_host.h> #include <linux/interrupt.h> +#include <linux/acpi.h>

#include <clocksource/arm_arch_timer.h> #include <asm/arch_timer.h> @@ -274,15 +275,10 @@ static const struct of_device_id arch_timer_of_match[] = { {}, };

-int kvm_timer_hyp_init(void) +static int kvm_of_timer_hyp_init(unsigned int *ppi) { struct device_node *np; - unsigned int ppi; - int err; - - timecounter = arch_timer_get_timecounter(); - if (!timecounter) - return -ENODEV; + int err = 0;

np = of_find_matching_node(NULL, arch_timer_of_match); if (!np) { @@ -290,19 +286,70 @@ int kvm_timer_hyp_init(void) return -ENODEV; }

- ppi = irq_of_parse_and_map(np, 2); - if (!ppi) { + *ppi = irq_of_parse_and_map(np, 2); + if (!(*ppi)) { kvm_err("kvm_arch_timer: no virtual timer interrupt\n"); err = -EINVAL; - goto out; - } + } else + kvm_info("%s IRQ%d\n", np->name, *ppi); + + of_node_put(np); + return err; +} + +#ifdef CONFIG_ACPI +static struct acpi_table_gtdt *gtdt_acpi; + +static int arch_timer_acpi_parse(struct acpi_table_header *table) +{ + gtdt_acpi = (struct acpi_table_gtdt *)table; + return 0; +} + +static int kvm_acpi_timer_hyp_init(unsigned int *ppi) +{ + /* The virtual timer interrupt was already + * registered during initialization with ACPI. + * Get the interrupt number from the tables + * and point there. + */ + acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_parse); + if (!gtdt_acpi) + return -ENODEV; + if (!gtdt_acpi->virtual_timer_interrupt) + return -EINVAL; + + *ppi = gtdt_acpi->virtual_timer_interrupt; + kvm_info("timer IRQ%d\n", *ppi); + return 0; +} +#else +static int kvm_acpi_timer_hyp_init(unsigned int *ppi) +{ + return -ENODEV; +} +#endif + +int kvm_timer_hyp_init(void) +{ + unsigned int ppi; + int err; + + timecounter = arch_timer_get_timecounter(); + if (!timecounter) + return -ENODEV; + + err = acpi_disabled ? kvm_of_timer_hyp_init(&ppi) : + kvm_acpi_timer_hyp_init(&ppi); + if (err) + return err;

err = request_percpu_irq(ppi, kvm_arch_timer_handler, "kvm guest timer", kvm_get_running_vcpus()); if (err) { kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n", ppi, err); - goto out; + return err; }

host_vtimer_irq = ppi; @@ -319,14 +366,11 @@ int kvm_timer_hyp_init(void) goto out_free; }

- kvm_info("%s IRQ%d\n", np->name, ppi); on_each_cpu(kvm_timer_init_interrupt, NULL, 1);

- goto out; + return 0; out_free: free_percpu_irq(ppi, kvm_get_running_vcpus()); -out: - of_node_put(np); return err; }

From: Narinder ndhillon@caviumnetworks.com

Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/kernel/topology.c | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index fcb8f7b..8ca4ab2 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -258,12 +258,19 @@ void store_cpu_topology(unsigned int cpuid) cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) | MPIDR_AFFINITY_LEVEL(mpidr, 3) << 8; } else { +#ifdef CONFIG_ACPI + /* Multiprocessor system : Single-thread per core */ + cpuid_topo->thread_id = -1; + cpuid_topo->core_id = (((mpidr >> 8) & 0xff) * 16) + (mpidr & 0xff); + cpuid_topo->cluster_id = (cpuid_topo->core_id) > 47 ? 1:0; +#else /* Multiprocessor system : Single-thread per core */ cpuid_topo->thread_id = -1; cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8 | MPIDR_AFFINITY_LEVEL(mpidr, 3) << 16; +#endif }

pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n",

From: Robert Richter rrichter@cavium.com

Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/kernel/topology.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 8ca4ab2..3f14ae9 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -11,6 +11,7 @@ * for more details. */

+#include <linux/acpi.h> #include <linux/cpu.h> #include <linux/cpumask.h> #include <linux/init.h> @@ -257,20 +258,20 @@ void store_cpu_topology(unsigned int cpuid) cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 1); cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 2) | MPIDR_AFFINITY_LEVEL(mpidr, 3) << 8; - } else { #ifdef CONFIG_ACPI + } else if (!acpi_disabled) { /* Multiprocessor system : Single-thread per core */ cpuid_topo->thread_id = -1; cpuid_topo->core_id = (((mpidr >> 8) & 0xff) * 16) + (mpidr & 0xff); cpuid_topo->cluster_id = (cpuid_topo->core_id) > 47 ? 1:0; -#else +#endif + } else { /* Multiprocessor system : Single-thread per core */ cpuid_topo->thread_id = -1; cpuid_topo->core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); cpuid_topo->cluster_id = MPIDR_AFFINITY_LEVEL(mpidr, 1) | MPIDR_AFFINITY_LEVEL(mpidr, 2) << 8 | MPIDR_AFFINITY_LEVEL(mpidr, 3) << 16; -#endif }

pr_debug("CPU%u: cluster %d core %d thread %d mpidr %#016llx\n",

From: Tomasz Nowicki tn@semihalf.com

ACPI spec5.1 states that the value of _CCA is inherited by all descendants of bus master devices, root PCI bridge in this case. So this patch is checking if PCI device's root bridge has coherency flag set and then mounts DMA ops (in similar way as DT does).

Signed-off-by: Tomasz Nowicki tn@semihalf.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/pci/pci-acpi.c | 13 +++++++++++++ drivers/pci/pci.c | 10 ++++++++++ drivers/pci/probe.c | 2 +- include/linux/pci-acpi.h | 2 ++ include/linux/pci.h | 2 ++ 5 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 314a625..9ba685c 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -291,6 +291,19 @@ int pci_get_hp_params(struct pci_dev *dev, struct hotplug_params *hpp) } EXPORT_SYMBOL_GPL(pci_get_hp_params);

+ +void pci_acpi_dma_configure(struct pci_dev *dev) +{ + struct device *bridge = pci_get_host_bridge_device(dev); + bool coherent; + + if (acpi_check_dma(ACPI_COMPANION(bridge), &coherent)) + arch_setup_dma_ops(&dev->dev, 0, 0, NULL, coherent); + + pci_put_host_bridge_device(bridge); +} +EXPORT_SYMBOL_GPL(pci_acpi_dma_configure); + /** * pci_acpi_wake_bus - Root bus wakeup notification fork function. * @work: Work item to handle. diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 0eec993..79c34d4 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -13,6 +13,7 @@ #include <linux/of.h> #include <linux/of_pci.h> #include <linux/pci.h> +#include <linux/pci-acpi.h> #include <linux/pm.h> #include <linux/slab.h> #include <linux/module.h> @@ -4539,6 +4540,15 @@ out: #endif #endif

+void pci_dma_configure(struct pci_dev *dev) +{ + if (acpi_disabled) + of_pci_dma_configure(dev); + else + pci_acpi_dma_configure(dev); +} +EXPORT_SYMBOL(pci_dma_configure); + /** * pci_ext_cfg_avail - can we access extended PCI config space? * diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 11ec2e7..9fad896 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1557,7 +1557,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) dev->dev.dma_mask = &dev->dma_mask; dev->dev.dma_parms = &dev->dma_parms; dev->dev.coherent_dma_mask = 0xffffffffull; - of_pci_dma_configure(dev); + pci_dma_configure(dev);

pci_set_dma_max_seg_size(dev, 65536); pci_set_dma_seg_boundary(dev, 0xffffffff); diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h index a965efa..786d929 100644 --- a/include/linux/pci-acpi.h +++ b/include/linux/pci-acpi.h @@ -54,6 +54,7 @@ static inline acpi_handle acpi_pci_get_bridge_handle(struct pci_bus *pbus)

void acpi_pci_add_bus(struct pci_bus *bus); void acpi_pci_remove_bus(struct pci_bus *bus); +void pci_acpi_dma_configure(struct pci_dev *dev);

#ifdef CONFIG_ACPI_PCI_SLOT void acpi_pci_slot_init(void); @@ -85,6 +86,7 @@ extern const u8 pci_acpi_dsm_uuid[]; #else /* CONFIG_ACPI */ static inline void acpi_pci_add_bus(struct pci_bus *bus) { } static inline void acpi_pci_remove_bus(struct pci_bus *bus) { } +static inline void pci_acpi_dma_configure(struct pci_dev *dev) { } #endif /* CONFIG_ACPI */

#ifdef CONFIG_ACPI_APEI diff --git a/include/linux/pci.h b/include/linux/pci.h index 7474225..3732cad 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -1336,6 +1336,7 @@ static inline void pci_bus_assign_domain_nr(struct pci_bus *bus, typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags); void pci_register_set_vga_state(arch_set_vga_state_t func); +void pci_dma_configure(struct pci_dev *dev);

#else /* CONFIG_PCI is not enabled */

@@ -1439,6 +1440,7 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus, static inline int pci_domain_nr(struct pci_bus *bus) { return 0; } static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; } static inline int pci_get_new_domain_nr(void) { return -ENOSYS; } +static inline void pci_dma_configure(struct pci_dev *dev) { }

#define dev_is_pci(d) (false) #define dev_is_pf(d) (false)

Fix build issue in case CONFIG_ACPI is not set.

Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/pci/pci.c | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 79c34d4..a73dd56 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4490,10 +4490,12 @@ void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent) static int use_dt_domains = -1; int domain;

+#ifdef CONFIG_ACPI if (!acpi_disabled) { domain = PCI_CONTROLLER(bus)->segment; goto out; } +#endif

domain = of_get_pci_domain_nr(parent->of_node);