From: Tirumalesh Chalamarla tchalamarla@caviumnetworks.com

Max its table size for ThunderX is 8MB (20 bits, 128 pages).

Currently the controller is detecting 16MB (256 pages). There is a bug in ITS (erratum 22375) that prevents S/W to set "0xff" (256 of 64KB pages) as the max table size of device table. This patch avoids setting page size to the maximum and also saves 8MB unnecessarily allocated memory.

Signed-off-by: Robert Richter rrichter@cavium.com Signed-off-by: Tirumalesh Chalamarla tchalamarla@caviumnetworks.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/Kconfig | 7 +++++++ drivers/irqchip/irq-gic-v3-its.c | 4 ++++ 2 files changed, 11 insertions(+)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 68ef1f1..af502e0 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -243,6 +243,13 @@ config ARCH_THUNDER help This enables support for Cavium's Thunder Family of SoCs.

+config THUNDERX_PASS1_ERRATA_22375 + bool "Cavium ThunderX erratum 22375" + depends on ARCH_THUNDER + def_bool ARCH_THUNDER + help + Enable workaround for erratum 22375. + config THUNDERX_PASS1_ERRATA_24313 bool "Cavium ThunderX erratum 24313" depends on ARCH_THUNDER diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index a46040f..36b664c 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -829,8 +829,12 @@ static int its_alloc_tables(struct its_node *its) * For other tables, only allocate a single page. */ if (type == GITS_BASER_TYPE_DEVICE) { +#ifdef CONFIG_THUNDERX_PASS1_ERRATA_22375 + u32 ids = 0x13; /* 20 bits, 8MB */ +#else u64 typer = readq_relaxed(its->base + GITS_TYPER); u32 ids = GITS_TYPER_DEVBITS(typer); +#endif

/* * 'order' was initialized earlier to the default page

From: David Daney david.daney@cavium.com

... and use is to force only_one_child() to return true.

Needed because the ThunderX PCIe RC cannot be identified by existing methods.

Signed-off-by: David Daney david.daney@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/pci/probe.c | 2 ++ include/linux/pci.h | 1 + 2 files changed, 3 insertions(+)

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index cefd636..11ec2e7 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1643,6 +1643,8 @@ static int only_one_child(struct pci_bus *bus) { struct pci_dev *parent = bus->self;

+ if (bus->is_pcierc) + return 1; if (!parent || !pci_is_pcie(parent)) return 0; if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT) diff --git a/include/linux/pci.h b/include/linux/pci.h index 8a0321a..1f1ce73 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -473,6 +473,7 @@ struct pci_bus { struct bin_attribute *legacy_io; /* legacy I/O for this bus */ struct bin_attribute *legacy_mem; /* legacy mem */ unsigned int is_added:1; + unsigned int is_pcierc:1; };

#define to_pci_bus(n) container_of(n, struct pci_bus, dev)

From: David Daney david.daney@cavium.com

The default is to continue doing the what we have done before, but add a hook so that this can be overridden.

Signed-off-by: David Daney david.daney@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- arch/arm64/include/asm/pci.h | 3 +++ arch/arm64/kernel/pci.c | 10 ++++++++++ 2 files changed, 13 insertions(+)

diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h index b008a72..ad3fb18 100644 --- a/arch/arm64/include/asm/pci.h +++ b/arch/arm64/include/asm/pci.h @@ -37,6 +37,9 @@ static inline int pci_proc_domain(struct pci_bus *bus) { return 1; } + +void set_pcibios_add_device(int (*arg)(struct pci_dev *)); + #endif /* CONFIG_PCI */

#endif /* __KERNEL__ */ diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index 4095379..3356023 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -38,11 +38,21 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res, return res->start; }

+static int (*pcibios_add_device_impl)(struct pci_dev *); + +void set_pcibios_add_device(int (*arg)(struct pci_dev *)) +{ + pcibios_add_device_impl = arg; +} + /* * Try to assign the IRQ number from DT when adding a new device */ int pcibios_add_device(struct pci_dev *dev) { + if (pcibios_add_device_impl) + return pcibios_add_device_impl(dev); + dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);

return 0;

From: Tirumalesh Chalamarla tchalamarla@caviumnetworks.com

Signed-off-by: David Daney david.daney@cavium.com Signed-off-by: Tirumalesh Chalamarla tchalamarla@caviumnetworks.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/pci/host/Kconfig | 12 + drivers/pci/host/Makefile | 2 + drivers/pci/host/pcie-thunder-pem.c | 462 ++++++++++++++++++++++++++++++++++++ drivers/pci/host/pcie-thunder.c | 423 +++++++++++++++++++++++++++++++++ 4 files changed, 899 insertions(+) create mode 100644 drivers/pci/host/pcie-thunder-pem.c create mode 100644 drivers/pci/host/pcie-thunder.c

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig index c132bdd..06e26ad 100644 --- a/drivers/pci/host/Kconfig +++ b/drivers/pci/host/Kconfig @@ -145,4 +145,16 @@ config PCIE_IPROC_BCMA Say Y here if you want to use the Broadcom iProc PCIe controller through the BCMA bus interface

+config PCI_THUNDER_PEM + bool + +config PCI_THUNDER + bool "Thunder PCIe host controller" + depends on ARM64 || COMPILE_TEST + depends on OF_PCI + select PCI_MSI + select PCI_THUNDER_PEM + help + Say Y here if you want internal PCI support on Thunder SoC. + endmenu diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile index 140d66f..a355155 100644 --- a/drivers/pci/host/Makefile +++ b/drivers/pci/host/Makefile @@ -17,3 +17,5 @@ obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o obj-$(CONFIG_PCIE_IPROC) += pcie-iproc.o obj-$(CONFIG_PCIE_IPROC_PLATFORM) += pcie-iproc-platform.o obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o +obj-$(CONFIG_PCI_THUNDER) += pcie-thunder.o +obj-$(CONFIG_PCI_THUNDER_PEM) += pcie-thunder-pem.o diff --git a/drivers/pci/host/pcie-thunder-pem.c b/drivers/pci/host/pcie-thunder-pem.c new file mode 100644 index 0000000..7861a8a --- /dev/null +++ b/drivers/pci/host/pcie-thunder-pem.c @@ -0,0 +1,462 @@ +/* + * PCIe host controller driver for Cavium Thunder SOC + * + * Copyright (C) 2014,2015 Cavium Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ +/* #define DEBUG 1 */ +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/delay.h> +#include <linux/irq.h> +#include <linux/pci.h> +#include <linux/irqdomain.h> +#include <linux/msi.h> +#include <linux/irqchip/arm-gic-v3.h> + +#define THUNDER_SLI_S2M_REG_ACC_BASE 0x874001000000ull + +#define THUNDER_GIC 0x801000000000ull +#define THUNDER_GICD_SETSPI_NSR 0x801000000040ull +#define THUNDER_GICD_CLRSPI_NSR 0x801000000048ull + +#define THUNDER_GSER_PCIE_MASK 0x01 + +#define PEM_CTL_STATUS 0x000 +#define PEM_RD_CFG 0x030 +#define P2N_BAR0_START 0x080 +#define P2N_BAR1_START 0x088 +#define P2N_BAR2_START 0x090 +#define BAR_CTL 0x0a8 +#define BAR2_MASK 0x0b0 +#define BAR1_INDEX 0x100 +#define PEM_CFG 0x410 +#define PEM_ON 0x420 + +struct thunder_pem { + struct list_head list; /* on thunder_pem_buses */ + bool connected; + unsigned int id; + unsigned int sli; + unsigned int sli_group; + unsigned int node; + u64 sli_window_base; + void __iomem *bar0; + void __iomem *bar4; + void __iomem *sli_s2m; + void __iomem *cfgregion; + struct pci_bus *bus; + int vwire_irqs[4]; + u32 vwire_data[4]; +}; + +static LIST_HEAD(thunder_pem_buses); + +static struct pci_device_id thunder_pem_pci_table[] = { + {PCI_VENDOR_ID_CAVIUM, 0xa020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, + {0,} +}; +MODULE_DEVICE_TABLE(pci, thunder_pem_pci_table); + +enum slix_s2m_ctype { + CTYPE_MEMORY = 0, + CTYPE_CONFIG = 1, + CTYPE_IO = 2 +}; + +static u64 slix_s2m_reg_val(unsigned mac, enum slix_s2m_ctype ctype, + bool merge, bool relaxed, bool snoop, u32 ba_msb) +{ + u64 v; + + v = (u64)(mac % 3) << 49; + v |= (u64)ctype << 53; + if (!merge) + v |= 1ull << 48; + if (relaxed) + v |= 5ull << 40; + if (!snoop) + v |= 5ull << 41; + v |= (u64)ba_msb; + + return v; +} + +static u32 thunder_pcierc_config_read(struct thunder_pem *pem, u32 reg, int size) +{ + unsigned int val; + + writeq(reg & ~3u, pem->bar0 + PEM_RD_CFG); + val = readq(pem->bar0 + PEM_RD_CFG) >> 32; + + if (size == 1) + val = (val >> (8 * (reg & 3))) & 0xff; + else if (size == 2) + val = (val >> (8 * (reg & 3))) & 0xffff; + + return val; +} + +static int thunder_pem_read_config(struct pci_bus *bus, unsigned int devfn, + int reg, int size, u32 *val) +{ + void __iomem *addr; + struct thunder_pem *pem = bus->sysdata; + unsigned int busnr = bus->number; + + if (busnr > 255 || devfn > 255 || reg > 4095) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = pem->cfgregion + ((busnr << 24) | (devfn << 16) | reg); + + switch (size) { + case 1: + *val = readb(addr); + break; + case 2: + *val = readw(addr); + break; + case 4: + *val = readl(addr); + break; + default: + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int thunder_pem_write_config(struct pci_bus *bus, unsigned int devfn, + int reg, int size, u32 val) +{ + void __iomem *addr; + struct thunder_pem *pem = bus->sysdata; + unsigned int busnr = bus->number; + + if (busnr > 255 || devfn > 255 || reg > 4095) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = pem->cfgregion + ((busnr << 24) | (devfn << 16) | reg); + + switch (size) { + case 1: + writeb(val, addr); + break; + case 2: + writew(val, addr); + break; + case 4: + writel(val, addr); + break; + default: + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops thunder_pem_ops = { + .read = thunder_pem_read_config, + .write = thunder_pem_write_config, +}; + +static struct thunder_pem *thunder_pem_from_dev(struct pci_dev *dev) +{ + struct thunder_pem *pem; + struct pci_bus *bus = dev->bus; + + while (!pci_is_root_bus(bus)) + bus = bus->parent; + + list_for_each_entry(pem, &thunder_pem_buses, list) { + if (pem->bus == bus) + return pem; + } + return NULL; +} + +int thunder_pem_requester_id(struct pci_dev *dev) +{ + struct thunder_pem *pem = thunder_pem_from_dev(dev); + + if (!pem) + return -ENODEV; + + if (pem->id < 3) + return ((1 << 16) | + ((dev)->bus->number << 8) | + (dev)->devfn); + + if (pem->id < 6) + return ((3 << 16) | + ((dev)->bus->number << 8) | + (dev)->devfn); + + if (pem->id < 9) + return ((1 << 19) | (1 << 16) | + ((dev)->bus->number << 8) | + (dev)->devfn); + + if (pem->id < 12) + return ((1 << 19) | + (3 << 16) | + ((dev)->bus->number << 8) | + (dev)->devfn); + return -ENODEV; +} + +static int thunder_pem_pcibios_add_device(struct pci_dev *dev) +{ + struct thunder_pem *pem; + u8 pin; + + pem = thunder_pem_from_dev(dev); + if (!pem) + return 0; + + pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); + + /* Cope with illegal. */ + if (pin > 4) + pin = 1; + + dev->irq = pin > 0 ? pem->vwire_irqs[pin - 1] : 0; + + if (pin) + dev_dbg(&dev->dev, "assigning IRQ %02d\n", dev->irq); + + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); + + return 0; +} + +static int thunder_pem_pci_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + struct thunder_pem *pem; + resource_size_t bar0_start; + u64 regval; + u64 sliaddr, pciaddr; + u32 cfgval; + int primary_bus; + int i; + int ret = 0; + struct resource *res; + LIST_HEAD(resources); + + set_pcibios_add_device(thunder_pem_pcibios_add_device); + + pem = devm_kzalloc(&pdev->dev, sizeof(*pem), GFP_KERNEL); + if (!pem) + return -ENOMEM; + + pci_set_drvdata(pdev, pem); + + bar0_start = pci_resource_start(pdev, 0); + pem->node = (bar0_start >> 44) & 3; + pem->id = ((bar0_start >> 24) & 7) + (6 * pem->node); + pem->sli = pem->id % 3; + pem->sli_group = (pem->id / 3) % 2; + pem->sli_window_base = 0x880000000000ull | (((u64)pem->node) << 44) | ((u64)pem->sli_group << 40); + pem->sli_window_base += 0x4000000000 * pem->sli; + + ret = pci_enable_device_mem(pdev); + if (ret) + goto out; + + pem->bar0 = pcim_iomap(pdev, 0, 0x100000); + if (!pem->bar0) { + ret = -ENOMEM; + goto out; + } + + pem->bar4 = pcim_iomap(pdev, 4, 0x100000); + if (!pem->bar0) { + ret = -ENOMEM; + goto out; + } + + sliaddr = THUNDER_SLI_S2M_REG_ACC_BASE | ((u64)pem->node << 44) | ((u64)pem->sli_group << 36); + + regval = readq(pem->bar0 + PEM_ON); + if (!(regval & 1)) { + dev_notice(&pdev->dev, "PEM%u_ON not set, skipping...\n", pem->id); + goto out; + } + + regval = readq(pem->bar0 + PEM_CTL_STATUS); + regval |= 0x10; /* Set Link Enable bit */ + writeq(regval, pem->bar0 + PEM_CTL_STATUS); + + udelay(1000); + + cfgval = thunder_pcierc_config_read(pem, 32 * 4, 4); /* PCIERC_CFG032 */ + + if (((cfgval >> 29 & 0x1) == 0x0) || ((cfgval >> 27 & 0x1) == 0x1)) { + dev_notice(&pdev->dev, "PEM%u Link Timeout, skipping...\n", pem->id); + goto out; + } + + pem->sli_s2m = devm_ioremap(&pdev->dev, sliaddr, 0x1000); + if (!pem->sli_s2m) { + ret = -ENOMEM; + goto out; + } + + pem->cfgregion = devm_ioremap(&pdev->dev, pem->sli_window_base, 0x100000000ull); + if (!pem->cfgregion) { + ret = -ENOMEM; + goto out; + } + regval = slix_s2m_reg_val(pem->sli, CTYPE_CONFIG, false, false, false, 0); + writeq(regval, pem->sli_s2m + 0x10 * ((0x40 * pem->sli) + 0)); + + cfgval = thunder_pcierc_config_read(pem, 6 * 4, 4); /* PCIERC_CFG006 */ + primary_bus = (cfgval >> 8) & 0xff; + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) { + ret = -ENOMEM; + goto out; + } + res->start = primary_bus; + res->end = 255; + res->flags = IORESOURCE_BUS; + pci_add_resource(&resources, res); + + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) { + ret = -ENOMEM; + goto out; + } + res->start = 0x100000 * pem->id; + res->end = res->start + 0x100000 - 1; + res->flags = IORESOURCE_IO; + pci_add_resource(&resources, res); + regval = slix_s2m_reg_val(pem->sli, CTYPE_IO, false, false, false, 0); + writeq(regval, pem->sli_s2m + 0x10 * ((0x40 * pem->sli) + 1)); + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) { + ret = -ENOMEM; + goto out; + } + pciaddr = 0x10000000ull; + res->start = pem->sli_window_base + 0x1000000000ull + pciaddr; + res->end = res->start + 0x1000000000ull - pciaddr - 1; + res->flags = IORESOURCE_MEM; + pci_add_resource_offset(&resources, res, res->start - pciaddr); + for (i = 0; i < 16; i++) { + regval = slix_s2m_reg_val(pem->sli, CTYPE_MEMORY, false, false, false, i); + writeq(regval, pem->sli_s2m + 0x10 * ((0x40 * pem->sli) + (0x10 + i))); + } + + res = kzalloc(sizeof(*res), GFP_KERNEL); + if (!res) { + ret = -ENOMEM; + goto out; + } + pciaddr = 0x1000000000ull; + res->start = pem->sli_window_base + 0x1000000000ull + pciaddr; + res->end = res->start + 0x1000000000ull - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + pci_add_resource_offset(&resources, res, res->start - pciaddr); + for (i = 0; i < 16; i++) { + regval = slix_s2m_reg_val(pem->sli, CTYPE_MEMORY, true, true, true, i + 0x10); + writeq(regval, pem->sli_s2m + 0x10 * ((0x40 * pem->sli) + (0x20 + i))); + } + + writeq(0, pem->bar0 + P2N_BAR0_START); + writeq(0, pem->bar0 + P2N_BAR1_START); + writeq(0, pem->bar0 + P2N_BAR2_START); + + regval = 0x10; /* BAR_CTL[BAR1_SIZ] = 1 (64MB) */ + regval |= 0x8; /* BAR_CTL[BAR2_ENB] = 1 */ + writeq(regval, pem->bar0 + BAR_CTL); + + /* 1st 4MB region -> GIC registers so 32-bit MSI can reach the GIC. */ + regval = (THUNDER_GIC + (((u64)pem->node) << 44)) >> 18; + /* BAR1_INDEX[ADDR_V] = 1 */ + regval |= 1; + writeq(regval, pem->bar0 + BAR1_INDEX); + /* Remaining regions linear mapping to physical address space */ + for (i = 1; i < 16; i++) { + regval = (i << 4) | 1; + writeq(regval, pem->bar0 + BAR1_INDEX + 8 * i); + } + + pem->bus = pci_create_root_bus(&pdev->dev, primary_bus, &thunder_pem_ops, pem, &resources); + if (!pem->bus) { + ret = -ENODEV; + goto err_root_bus; + } + pem->bus->is_pcierc = 1; + list_add_tail(&pem->list, &thunder_pem_buses); + + for (i = 0; i < 3; i++) { + pem->vwire_data[i] = 40 + 4 * pem->id + i; + pem->vwire_irqs[i] = irq_create_mapping(gic_get_irq_domain(), pem->vwire_data[i]); + if (!pem->vwire_irqs[i]) { + dev_err(&pdev->dev, "Error: No irq mapping for %u\n", pem->vwire_data[i]); + continue; + } + irq_set_irq_type(pem->vwire_irqs[i], IRQ_TYPE_LEVEL_HIGH); + + writeq(THUNDER_GICD_SETSPI_NSR, pem->bar4 + 0 + (i + 2) * 32); + writeq(pem->vwire_data[i], pem->bar4 + 8 + (i + 2) * 32); + writeq(THUNDER_GICD_CLRSPI_NSR, pem->bar4 + 16 + (i + 2) * 32); + writeq(pem->vwire_data[i], pem->bar4 + 24 + (i + 2) * 32); + } + ret = pci_read_config_dword(pdev, 44 * 4, &cfgval); + if (WARN_ON(ret)) + goto err_free_root_bus; + cfgval &= ~0x40000000; /* Clear FUNM */ + cfgval |= 0x80000000; /* Set MSIXEN */ + pci_write_config_dword(pdev, 44 * 4, cfgval); + pem->bus->msi = pdev->bus->msi; + + pci_scan_child_bus(pem->bus); + pci_bus_add_devices(pem->bus); + pci_assign_unassigned_root_bus_resources(pem->bus); + + return 0; + +err_free_root_bus: + pci_remove_root_bus(pem->bus); +err_root_bus: + pci_free_resource_list(&resources); +out: + return ret; +} + +static void thunder_pem_pci_remove(struct pci_dev *pdev) +{ +} + +static struct pci_driver thunder_pem_driver = { + .name = "thunder_pem", + .id_table = thunder_pem_pci_table, + .probe = thunder_pem_pci_probe, + .remove = thunder_pem_pci_remove +}; + +static int __init thunder_pcie_init(void) +{ + int ret; + + ret = pci_register_driver(&thunder_pem_driver); + + return ret; +} +module_init(thunder_pcie_init); + +static void __exit thunder_pcie_exit(void) +{ + pci_unregister_driver(&thunder_pem_driver); +} +module_exit(thunder_pcie_exit); diff --git a/drivers/pci/host/pcie-thunder.c b/drivers/pci/host/pcie-thunder.c new file mode 100644 index 0000000..cbe4b44 --- /dev/null +++ b/drivers/pci/host/pcie-thunder.c @@ -0,0 +1,423 @@ +/* + * PCIe host controller driver for Cavium Thunder SOC + * + * Copyright (C) 2014, 2015 Cavium Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_irq.h> +#include <linux/of_pci.h> +#include <linux/pci.h> +#include <linux/platform_device.h> +#include <linux/msi.h> +#include <linux/irqchip/arm-gic-v3.h> + +#define PCI_DEVICE_ID_THUNDER_BRIDGE 0xa002 + +#define THUNDER_PCIE_BUS_SHIFT 20 +#define THUNDER_PCIE_DEV_SHIFT 15 +#define THUNDER_PCIE_FUNC_SHIFT 12 + +#define THUNDER_ECAM0_CFG_BASE 0x848000000000 +#define THUNDER_ECAM1_CFG_BASE 0x849000000000 +#define THUNDER_ECAM2_CFG_BASE 0x84a000000000 +#define THUNDER_ECAM3_CFG_BASE 0x84b000000000 +#define THUNDER_ECAM4_CFG_BASE 0x948000000000 +#define THUNDER_ECAM5_CFG_BASE 0x949000000000 +#define THUNDER_ECAM6_CFG_BASE 0x94a000000000 +#define THUNDER_ECAM7_CFG_BASE 0x94b000000000 + +struct thunder_pcie { + struct device_node *node; + struct device *dev; + void __iomem *cfg_base; + struct msi_controller *msi; + int ecam; + bool valid; +}; + +int thunder_pem_requester_id(struct pci_dev *dev); + +static atomic_t thunder_pcie_ecam_probed; + +static u32 pci_requester_id_ecam(struct pci_dev *dev) +{ + return (((pci_domain_nr(dev->bus) >> 2) << 19) | + ((pci_domain_nr(dev->bus) % 4) << 16) | + (dev->bus->number << 8) | dev->devfn); +} + +static u32 thunder_pci_requester_id(struct pci_dev *dev, u16 alias) +{ + int ret; + + ret = thunder_pem_requester_id(dev); + if (ret >= 0) + return (u32)ret; + + return pci_requester_id_ecam(dev); +} + +/* + * This bridge is just for the sake of supporting ARI for + * downstream devices. No resources are attached to it. + * Copy upstream root bus resources to bridge which aide in + * resource claiming for downstream devices + */ +static void pci_bridge_resource_fixup(struct pci_dev *dev) +{ + struct pci_bus *bus; + int resno; + + bus = dev->subordinate; + for (resno = 0; resno < PCI_BRIDGE_RESOURCE_NUM; resno++) { + bus->resource[resno] = pci_bus_resource_n(bus->parent, + PCI_BRIDGE_RESOURCE_NUM + resno); + } + + for (resno = PCI_BRIDGE_RESOURCES; + resno <= PCI_BRIDGE_RESOURCE_END; resno++) { + dev->resource[resno].start = dev->resource[resno].end = 0; + dev->resource[resno].flags = 0; + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BRIDGE, + pci_bridge_resource_fixup); + +/* + * All PCIe devices in Thunder have fixed resources, shouldn't be reassigned. + * Also claim the device's valid resources to set 'res->parent' hierarchy. + */ +static void pci_dev_resource_fixup(struct pci_dev *dev) +{ + struct resource *res; + int resno; + + /* + * If the ECAM is not yet probed, we must be in a virtual + * machine. In that case, don't mark things as + * IORESOURCE_PCI_FIXED + */ + if (!atomic_read(&thunder_pcie_ecam_probed)) + return; + + for (resno = 0; resno < PCI_NUM_RESOURCES; resno++) + dev->resource[resno].flags |= IORESOURCE_PCI_FIXED; + + for (resno = 0; resno < PCI_BRIDGE_RESOURCES; resno++) { + res = &dev->resource[resno]; + if (res->parent || !(res->flags & IORESOURCE_MEM)) + continue; + pci_claim_resource(dev, resno); + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, + pci_dev_resource_fixup); + +static void __iomem *thunder_pcie_get_cfg_addr(struct thunder_pcie *pcie, + unsigned int busnr, + unsigned int devfn, int reg) +{ + return pcie->cfg_base + + ((busnr << THUNDER_PCIE_BUS_SHIFT) + | (PCI_SLOT(devfn) << THUNDER_PCIE_DEV_SHIFT) + | (PCI_FUNC(devfn) << THUNDER_PCIE_FUNC_SHIFT)) + reg; +} + +static int thunder_pcie_read_config(struct pci_bus *bus, unsigned int devfn, + int reg, int size, u32 *val) +{ + struct thunder_pcie *pcie = bus->sysdata; + void __iomem *addr; + unsigned int busnr = bus->number; + + if (busnr > 255 || devfn > 255 || reg > 4095) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = thunder_pcie_get_cfg_addr(pcie, busnr, devfn, reg); + + switch (size) { + case 1: + *val = readb(addr); + break; + case 2: + *val = readw(addr); + break; + case 4: + *val = readl(addr); + break; + default: + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int thunder_pcie_write_config(struct pci_bus *bus, unsigned int devfn, + int reg, int size, u32 val) +{ + struct thunder_pcie *pcie = bus->sysdata; + void __iomem *addr; + unsigned int busnr = bus->number; + + if (busnr > 255 || devfn > 255 || reg > 4095) + return PCIBIOS_DEVICE_NOT_FOUND; + + addr = thunder_pcie_get_cfg_addr(pcie, busnr, devfn, reg); + + switch (size) { + case 1: + writeb(val, addr); + break; + case 2: + writew(val, addr); + break; + case 4: + writel(val, addr); + break; + default: + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops thunder_pcie_ops = { + .read = thunder_pcie_read_config, + .write = thunder_pcie_write_config, +}; + +static int thunder_pcie_msi_enable(struct thunder_pcie *pcie, + struct pci_bus *bus) +{ + struct device_node *msi_node; + + msi_node = of_parse_phandle(pcie->node, "msi-parent", 0); + if (!msi_node) + return -ENODEV; + + pcie->msi = of_pci_find_msi_chip_by_node(msi_node); + if (!pcie->msi) + return -ENODEV; + + pcie->msi->dev = pcie->dev; + bus->msi = pcie->msi; + + return 0; +} + +static void thunder_pcie_config(struct thunder_pcie *pcie, u64 addr) +{ + atomic_set(&thunder_pcie_ecam_probed, 1); + set_its_pci_requester_id(thunder_pci_requester_id); + + pcie->valid = true; + + switch (addr) { + case THUNDER_ECAM0_CFG_BASE: + pcie->ecam = 0; + break; + case THUNDER_ECAM1_CFG_BASE: + pcie->ecam = 1; + break; + case THUNDER_ECAM2_CFG_BASE: + pcie->ecam = 2; + break; + case THUNDER_ECAM3_CFG_BASE: + pcie->ecam = 3; + break; + case THUNDER_ECAM4_CFG_BASE: + pcie->ecam = 4; + break; + case THUNDER_ECAM5_CFG_BASE: + pcie->ecam = 5; + break; + case THUNDER_ECAM6_CFG_BASE: + pcie->ecam = 6; + break; + case THUNDER_ECAM7_CFG_BASE: + pcie->ecam = 7; + break; + default: + pcie->valid = false; + break; + } +} + +static int thunder_pcie_probe(struct platform_device *pdev) +{ + struct thunder_pcie *pcie; + struct resource *cfg_base; + struct pci_bus *bus; + int ret = 0; + LIST_HEAD(res); + + pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->node = of_node_get(pdev->dev.of_node); + pcie->dev = &pdev->dev; + + /* Get controller's configuration space range */ + cfg_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + thunder_pcie_config(pcie, cfg_base->start); + + pcie->cfg_base = devm_ioremap_resource(&pdev->dev, cfg_base); + if (IS_ERR(pcie->cfg_base)) { + ret = PTR_ERR(pcie->cfg_base); + goto err_ioremap; + } + + dev_info(&pdev->dev, "ECAM%d CFG BASE 0x%llx\n", + pcie->ecam, (u64)cfg_base->start); + + ret = of_pci_get_host_bridge_resources(pdev->dev.of_node, + 0, 255, &res, NULL); + if (ret) + goto err_root_bus; + + bus = pci_create_root_bus(&pdev->dev, 0, &thunder_pcie_ops, pcie, &res); + if (!bus) { + ret = -ENODEV; + goto err_root_bus; + } + + /* Set reference to MSI chip */ + ret = thunder_pcie_msi_enable(pcie, bus); + if (ret) { + dev_err(&pdev->dev, + "Unable to set reference to MSI chip: ret=%d\n", ret); + goto err_msi; + } + + platform_set_drvdata(pdev, pcie); + + pci_scan_child_bus(bus); + pci_bus_add_devices(bus); + + return 0; +err_msi: + pci_remove_root_bus(bus); +err_root_bus: + pci_free_resource_list(&res); +err_ioremap: + of_node_put(pcie->node); + return ret; +} + +static const struct of_device_id thunder_pcie_of_match[] = { + { .compatible = "cavium,thunder-pcie", }, + {}, +}; +MODULE_DEVICE_TABLE(of, thunder_pcie_of_match); + +static struct platform_driver thunder_pcie_driver = { + .driver = { + .name = "thunder-pcie", + .owner = THIS_MODULE, + .of_match_table = thunder_pcie_of_match, + }, + .probe = thunder_pcie_probe, +}; +module_platform_driver(thunder_pcie_driver); + +#ifdef CONFIG_ACPI + +static int +thunder_mmcfg_read_config(struct pci_mmcfg_region *cfg, unsigned int busnr, + unsigned int devfn, int reg, int len, u32 *value) +{ + struct thunder_pcie *pcie = cfg->data; + void __iomem *addr; + + if (!pcie->valid) { + /* Not support for now */ + pr_err("RC PEM not supported !!!\n"); + return PCIBIOS_DEVICE_NOT_FOUND; + } + + addr = thunder_pcie_get_cfg_addr(pcie, busnr, devfn, reg); + + switch (len) { + case 1: + *value = readb(addr); + break; + case 2: + *value = readw(addr); + break; + case 4: + *value = readl(addr); + break; + default: + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int thunder_mmcfg_write_config(struct pci_mmcfg_region *cfg, + unsigned int busnr, unsigned int devfn, int reg, int len, + u32 value) { + struct thunder_pcie *pcie = cfg->data; + void __iomem *addr; + + if (!pcie->valid) { + /* Not support for now */ + pr_err("RC PEM not supported !!!\n"); + return PCIBIOS_DEVICE_NOT_FOUND; + } + + addr = thunder_pcie_get_cfg_addr(pcie, busnr, devfn, reg); + + switch (len) { + case 1: + writeb(value, addr); + break; + case 2: + writew(value, addr); + break; + case 4: + writel(value, addr); + break; + default: + return PCIBIOS_BAD_REGISTER_NUMBER; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int thunder_acpi_mcfg_fixup(struct acpi_pci_root *root, + struct pci_mmcfg_region *cfg) +{ + struct thunder_pcie *pcie; + + pcie = kzalloc(sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->dev = &root->device->dev; + + thunder_pcie_config(pcie, cfg->address); + + pcie->cfg_base = cfg->virt; + cfg->data = pcie; + cfg->read = thunder_mmcfg_read_config; + cfg->write = thunder_mmcfg_write_config; + + return 0; +} +DECLARE_ACPI_MCFG_FIXUP("CAVIUM", "THUNDERX", thunder_acpi_mcfg_fixup); +#endif + +MODULE_AUTHOR("Sunil Goutham"); +MODULE_DESCRIPTION("Cavium Thunder ECAM host controller driver"); +MODULE_LICENSE("GPL v2"); +

From: Thanneeru Srinivasulu tsrinivasulu@caviumnetworks.com

Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/net/ethernet/cavium/thunder/thunder_bgx.c | 3 +++ drivers/net/ethernet/cavium/thunder/thunder_bgx.h | 1 + 2 files changed, 4 insertions(+)

diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c index 633ec05..6356323 100644 --- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.c +++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.c @@ -866,6 +866,9 @@ static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent) char bgx_sel[5]; u8 lmac;

+ /*Load octeon mdio driver*/ + octeon_mdiobus_force_mod_depencency(); + bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL); if (!bgx) return -ENOMEM; diff --git a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h index ba4f53b..c508114 100644 --- a/drivers/net/ethernet/cavium/thunder/thunder_bgx.h +++ b/drivers/net/ethernet/cavium/thunder/thunder_bgx.h @@ -180,6 +180,7 @@ enum MCAST_MODE { #define BCAST_ACCEPT 1 #define CAM_ACCEPT 1

+void octeon_mdiobus_force_mod_depencency(void); void bgx_add_dmac_addr(u64 dmac, int node, int bgx_idx, int lmac); unsigned bgx_get_map(int node); int bgx_get_lmac_count(int node, int bgx);

From: Radha Mohan Chintakuntla rchintakuntla@cavium.com

This patch modifies the mdio-octeon driver to work on both ThunderX and Octeon SoCs from Cavium Inc.

Signed-off-by: Sunil Goutham sgoutham@cavium.com Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Signed-off-by: David Daney david.daney@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/net/phy/Kconfig | 9 ++-- drivers/net/phy/mdio-octeon.c | 122 ++++++++++++++++++++++++++++++++++++------ 2 files changed, 111 insertions(+), 20 deletions(-)

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index cf18940..0d6af19 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -145,13 +145,14 @@ config MDIO_GPIO will be called mdio-gpio.

config MDIO_OCTEON - tristate "Support for MDIO buses on Octeon SOCs" - depends on CAVIUM_OCTEON_SOC + tristate "Support for MDIO buses on Octeon and ThunderX SOCs" + depends on 64BIT default y help

- This module provides a driver for the Octeon MDIO busses. - It is required by the Octeon Ethernet device drivers. + This module provides a driver for the Octeon and ThunderX MDIO + busses. It is required by the Octeon and ThunderX ethernet device + drivers.

If in doubt, say Y.

diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c index c838ad6..507aade 100644 --- a/drivers/net/phy/mdio-octeon.c +++ b/drivers/net/phy/mdio-octeon.c @@ -7,6 +7,7 @@ */

#include <linux/platform_device.h> +#include <linux/of_address.h> #include <linux/of_mdio.h> #include <linux/delay.h> #include <linux/module.h> @@ -14,11 +15,12 @@ #include <linux/phy.h> #include <linux/io.h>

+#ifdef CONFIG_CAVIUM_OCTEON_SOC #include <asm/octeon/octeon.h> -#include <asm/octeon/cvmx-smix-defs.h> +#endif

-#define DRV_VERSION "1.0" -#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver" +#define DRV_VERSION "1.1" +#define DRV_DESCRIPTION "Cavium Networks Octeon/ThunderX SMI/MDIO driver"

#define SMI_CMD 0x0 #define SMI_WR_DAT 0x8 @@ -26,6 +28,79 @@ #define SMI_CLK 0x18 #define SMI_EN 0x20

+#ifdef __BIG_ENDIAN_BITFIELD +#define OCT_MDIO_BITFIELD_FIELD(field, more) \ + field; \ + more + +#else +#define OCT_MDIO_BITFIELD_FIELD(field, more) \ + more \ + field; + +#endif + +union cvmx_smix_clk { + uint64_t u64; + struct cvmx_smix_clk_s { + OCT_MDIO_BITFIELD_FIELD(u64 reserved_25_63:39, + OCT_MDIO_BITFIELD_FIELD(u64 mode:1, + OCT_MDIO_BITFIELD_FIELD(u64 reserved_21_23:3, + OCT_MDIO_BITFIELD_FIELD(u64 sample_hi:5, + OCT_MDIO_BITFIELD_FIELD(u64 sample_mode:1, + OCT_MDIO_BITFIELD_FIELD(u64 reserved_14_14:1, + OCT_MDIO_BITFIELD_FIELD(u64 clk_idle:1, + OCT_MDIO_BITFIELD_FIELD(u64 preamble:1, + OCT_MDIO_BITFIELD_FIELD(u64 sample:4, + OCT_MDIO_BITFIELD_FIELD(u64 phase:8, + ;)))))))))) + } s; +}; + +union cvmx_smix_cmd { + uint64_t u64; + struct cvmx_smix_cmd_s { + OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46, + OCT_MDIO_BITFIELD_FIELD(u64 phy_op:2, + OCT_MDIO_BITFIELD_FIELD(u64 reserved_13_15:3, + OCT_MDIO_BITFIELD_FIELD(u64 phy_adr:5, + OCT_MDIO_BITFIELD_FIELD(u64 reserved_5_7:3, + OCT_MDIO_BITFIELD_FIELD(u64 reg_adr:5, + ;)))))) + } s; +}; + +union cvmx_smix_en { + uint64_t u64; + struct cvmx_smix_en_s { + OCT_MDIO_BITFIELD_FIELD(u64 reserved_1_63:63, + OCT_MDIO_BITFIELD_FIELD(u64 en:1, + ;)) + } s; +}; + +union cvmx_smix_rd_dat { + uint64_t u64; + struct cvmx_smix_rd_dat_s { + OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46, + OCT_MDIO_BITFIELD_FIELD(u64 pending:1, + OCT_MDIO_BITFIELD_FIELD(u64 val:1, + OCT_MDIO_BITFIELD_FIELD(u64 dat:16, + ;)))) + } s; +}; + +union cvmx_smix_wr_dat { + uint64_t u64; + struct cvmx_smix_wr_dat_s { + OCT_MDIO_BITFIELD_FIELD(u64 reserved_18_63:46, + OCT_MDIO_BITFIELD_FIELD(u64 pending:1, + OCT_MDIO_BITFIELD_FIELD(u64 val:1, + OCT_MDIO_BITFIELD_FIELD(u64 dat:16, + ;)))) + } s; +}; + enum octeon_mdiobus_mode { UNINIT = 0, C22, @@ -41,6 +116,21 @@ struct octeon_mdiobus { int phy_irq[PHY_MAX_ADDR]; };

+#ifdef CONFIG_CAVIUM_OCTEON_SOC +static void oct_mdio_writeq(u64 val, u64 addr) +{ + cvmx_write_csr(addr, val); +} + +static u64 oct_mdio_readq(u64 addr) +{ + return cvmx_read_csr(addr); +} +#else +#define oct_mdio_writeq(val, addr) writeq_relaxed(val, (void *)addr) +#define oct_mdio_readq(addr) readq_relaxed((void *)addr) +#endif + static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p, enum octeon_mdiobus_mode m) { @@ -49,10 +139,10 @@ static void octeon_mdiobus_set_mode(struct octeon_mdiobus *p, if (m == p->mode) return;

- smi_clk.u64 = cvmx_read_csr(p->register_base + SMI_CLK); + smi_clk.u64 = oct_mdio_readq(p->register_base + SMI_CLK); smi_clk.s.mode = (m == C45) ? 1 : 0; smi_clk.s.preamble = 1; - cvmx_write_csr(p->register_base + SMI_CLK, smi_clk.u64); + oct_mdio_writeq(smi_clk.u64, p->register_base + SMI_CLK); p->mode = m; }

@@ -67,7 +157,7 @@ static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p,

smi_wr.u64 = 0; smi_wr.s.dat = regnum & 0xffff; - cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64); + oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);

regnum = (regnum >> 16) & 0x1f;

@@ -75,14 +165,14 @@ static int octeon_mdiobus_c45_addr(struct octeon_mdiobus *p, smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_45_ADDRESS */ smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); + oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

do { /* Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ __delay(1000); - smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT); + smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT); } while (smi_wr.s.pending && --timeout);

if (timeout <= 0) @@ -114,14 +204,14 @@ static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum) smi_cmd.s.phy_op = op; smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); + oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

do { /* Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ __delay(1000); - smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT); + smi_rd.u64 = oct_mdio_readq(p->register_base + SMI_RD_DAT); } while (smi_rd.s.pending && --timeout);

if (smi_rd.s.val) @@ -153,20 +243,20 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,

smi_wr.u64 = 0; smi_wr.s.dat = val; - cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64); + oct_mdio_writeq(smi_wr.u64, p->register_base + SMI_WR_DAT);

smi_cmd.u64 = 0; smi_cmd.s.phy_op = op; smi_cmd.s.phy_adr = phy_id; smi_cmd.s.reg_adr = regnum; - cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64); + oct_mdio_writeq(smi_cmd.u64, p->register_base + SMI_CMD);

do { /* Wait 1000 clocks so we don't saturate the RSL bus * doing reads. */ __delay(1000); - smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT); + smi_wr.u64 = oct_mdio_readq(p->register_base + SMI_WR_DAT); } while (smi_wr.s.pending && --timeout);

if (timeout <= 0) @@ -210,7 +300,7 @@ static int octeon_mdiobus_probe(struct platform_device *pdev)

smi_en.u64 = 0; smi_en.s.en = 1; - cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); + oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN);

bus->mii_bus->priv = bus; bus->mii_bus->irq = bus->phy_irq; @@ -234,7 +324,7 @@ fail_register: mdiobus_free(bus->mii_bus); fail: smi_en.u64 = 0; - cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); + oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN); return err; }

@@ -248,7 +338,7 @@ static int octeon_mdiobus_remove(struct platform_device *pdev) mdiobus_unregister(bus->mii_bus); mdiobus_free(bus->mii_bus); smi_en.u64 = 0; - cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64); + oct_mdio_writeq(smi_en.u64, bus->register_base + SMI_EN); return 0; }

From: Radha Mohan Chintakuntla rchintakuntla@cavium.com

The CONFIG_MDIO_OCTEON is required so that the ThunderX NIC driver can talk to the PHY drivers.

Signed-off-by: Radha Mohan Chintakuntla rchintakuntla@cavium.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/net/ethernet/cavium/Kconfig | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/drivers/net/ethernet/cavium/Kconfig b/drivers/net/ethernet/cavium/Kconfig index c4d6bbe..b756a00 100644 --- a/drivers/net/ethernet/cavium/Kconfig +++ b/drivers/net/ethernet/cavium/Kconfig @@ -37,6 +37,8 @@ config THUNDER_NIC_BGX tristate "Thunder MAC interface driver (BGX)" depends on 64BIT default ARCH_THUNDER + select PHYLIB + select MDIO_OCTEON ---help--- This driver supports programming and controlling of MAC interface from NIC physical function driver.

From: Ganapatrao Kulkarni gkulkarni@caviumnetworks.com

DT bindings for numa map for memory, cores and IOs using arm,associativity device node property.

Signed-off-by: Ganapatrao Kulkarni gkulkarni@caviumnetworks.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- Documentation/devicetree/bindings/arm/numa.txt | 212 +++++++++++++++++++++++++ 1 file changed, 212 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/numa.txt

diff --git a/Documentation/devicetree/bindings/arm/numa.txt b/Documentation/devicetree/bindings/arm/numa.txt new file mode 100644 index 0000000..dc3ef86 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/numa.txt @@ -0,0 +1,212 @@ +============================================================================== +NUMA binding description. +============================================================================== + +============================================================================== +1 - Introduction +============================================================================== + +Systems employing a Non Uniform Memory Access (NUMA) architecture contain +collections of hardware resources including processors, memory, and I/O buses, +that comprise what is commonly known as a NUMA node. +Processor accesses to memory within the local NUMA node is generally faster +than processor accesses to memory outside of the local NUMA node. +DT defines interfaces that allow the platform to convey NUMA node +topology information to OS. + +============================================================================== +2 - arm,associativity +============================================================================== +The mapping is done using arm,associativity device property. +this property needs to be present in every device node which needs to to be +mapped to numa nodes. + +arm,associativity property is set of 32-bit integers which defines level of +topology and boundary in the system at which a significant difference in +performance can be measured between cross-device accesses within +a single location and those spanning multiple locations. +The first cell always contains the broadest subdivision within the system, +while the last cell enumerates the individual devices, such as an SMT thread +of a CPU, or a bus bridge within an SoC". + +ex: + /* board 0, socket 0, cluster 0, core 0 thread 0 */ + arm,associativity = <0 0 0 0 0>; + +============================================================================== +3 - arm,associativity-reference-points +============================================================================== +This property is a set of 32-bit integers, each representing an index into +the arm,associativity nodes. The first integer is the most significant +NUMA boundary and the following are progressively less significant boundaries. +There can be more than one level of NUMA. + +Ex: + arm,associativity-reference-points = <0 1>; + The board Id(index 0) used first to calculate the associativity (node + distance), then follows the socket id(index 1). + + arm,associativity-reference-points = <1 0>; + The socket Id(index 1) used first to calculate the associativity, + then follows the board id(index 0). + + arm,associativity-reference-points = <0>; + Only the board Id(index 0) used to calculate the associativity. + + arm,associativity-reference-points = <1>; + Only socket Id(index 1) used to calculate the associativity. + +============================================================================== +4 - Example dts +============================================================================== + +Example: 2 Node system consists of 2 boards and each board having one socket +and 8 core in each socket. + + arm,associativity-reference-points = <0>; + + memory@00c00000 { + device_type = "memory"; + reg = <0x0 0x00c00000 0x0 0x80000000>; + /* board 0, socket 0, no specific core */ + arm,associativity = <0 0 0xffff>; + }; + + memory@10000000000 { + device_type = "memory"; + reg = <0x100 0x00000000 0x0 0x80000000>; + /* board 1, socket 0, no specific core */ + arm,associativity = <1 0 0xffff>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@000 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x000>; + enable-method = "psci"; + /* board 0, socket 0, core 0*/ + arm,associativity = <0 0 0>; + }; + cpu@001 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x001>; + enable-method = "psci"; + arm,associativity = <0 0 1>; + }; + cpu@002 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x002>; + enable-method = "psci"; + arm,associativity = <0 0 2>; + }; + cpu@003 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x003>; + enable-method = "psci"; + arm,associativity = <0 0 3>; + }; + cpu@004 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x004>; + enable-method = "psci"; + arm,associativity = <0 0 4>; + }; + cpu@005 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x005>; + enable-method = "psci"; + arm,associativity = <0 0 5>; + }; + cpu@006 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x006>; + enable-method = "psci"; + arm,associativity = <0 0 6>; + }; + cpu@007 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x007>; + enable-method = "psci"; + arm,associativity = <0 0 7>; + }; + cpu@008 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x008>; + enable-method = "psci"; + /* board 1, socket 0, core 0*/ + arm,associativity = <1 0 0>; + }; + cpu@009 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x009>; + enable-method = "psci"; + arm,associativity = <1 0 1>; + }; + cpu@00a { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x00a>; + enable-method = "psci"; + arm,associativity = <0 0 2>; + }; + cpu@00b { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x00b>; + enable-method = "psci"; + arm,associativity = <1 0 3>; + }; + cpu@00c { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x00c>; + enable-method = "psci"; + arm,associativity = <1 0 4>; + }; + cpu@00d { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x00d>; + enable-method = "psci"; + arm,associativity = <1 0 5>; + }; + cpu@00e { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x00e>; + enable-method = "psci"; + arm,associativity = <1 0 6>; + }; + cpu@00f { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x00f>; + enable-method = "psci"; + arm,associativity = <1 0 7>; + }; + }; + + pcie0: pcie0@0x8480,00000000 { + compatible = "arm,armv8"; + device_type = "pci"; + bus-range = <0 255>; + #size-cells = <2>; + #address-cells = <3>; + reg = <0x8480 0x00000000 0 0x10000000>; /* Configuration space */ + ranges = <0x03000000 0x8010 0x00000000 0x8010 0x00000000 0x70 0x00000000>; /* mem ranges */ + /* board 0, socket 0, pci bus 0*/ + arm,associativity = <0 0 0>; + };

From: Ganapatrao Kulkarni gkulkarni@caviumnetworks.com

Current efistub deletes the memory nodes from the dt before the dt file is passed to linux to avoid memblocks addition from dt early memory scan code.

This patch avoids the deletion and still makes sure the memory is not added from the dt code since, the memory info has to be used from efi tables.

Signed-off-by: Ganapatrao Kulkarni gkulkarni@caviumnetworks.com Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/firmware/efi/libstub/fdt.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/firmware/efi/libstub/fdt.c b/drivers/firmware/efi/libstub/fdt.c index ef5d764..ccdb24f 100644 --- a/drivers/firmware/efi/libstub/fdt.c +++ b/drivers/firmware/efi/libstub/fdt.c @@ -54,13 +54,15 @@ efi_status_t update_fdt(efi_system_table_t *sys_table, void *orig_fdt, goto fdt_set_fail;

/* - * Delete any memory nodes present. We must delete nodes which - * early_init_dt_scan_memory may try to use. + * Disable any memory nodes present by adding (or overriding) their + * linux,usable-memory property to (u32)0, which is interpreted as + * a zero sized memory range by the DT code. */ prev = 0; for (;;) { const char *type; int len; + static const u32 usable_memory = 0;

node = fdt_next_node(fdt, prev, NULL); if (node < 0) @@ -68,8 +70,10 @@ efi_status_t update_fdt(efi_system_table_t *sys_table, void *orig_fdt,

type = fdt_getprop(fdt, node, "device_type", &len); if (type && strncmp(type, "memory", len) == 0) { - fdt_del_node(fdt, node); - continue; + status = fdt_setprop(fdt, node, "linux,usable-memory", + &usable_memory, sizeof(u32)); + if (status) + goto fdt_set_fail; }

prev = node;

This reverts commit e6316f74ce6f149abf0112e040b0b0f4de089d80. Build issue fix.

Signed-off-by: Vadim Lomovtsev Vadim.Lomovtsev@caviumnetworks.com --- drivers/pci/host/pcie-thunder.c | 88 ----------------------------------------- 1 file changed, 88 deletions(-)

diff --git a/drivers/pci/host/pcie-thunder.c b/drivers/pci/host/pcie-thunder.c index cbe4b44..7428401 100644 --- a/drivers/pci/host/pcie-thunder.c +++ b/drivers/pci/host/pcie-thunder.c @@ -329,94 +329,6 @@ static struct platform_driver thunder_pcie_driver = { }; module_platform_driver(thunder_pcie_driver);

-#ifdef CONFIG_ACPI - -static int -thunder_mmcfg_read_config(struct pci_mmcfg_region *cfg, unsigned int busnr, - unsigned int devfn, int reg, int len, u32 *value) -{ - struct thunder_pcie *pcie = cfg->data; - void __iomem *addr; - - if (!pcie->valid) { - /* Not support for now */ - pr_err("RC PEM not supported !!!\n"); - return PCIBIOS_DEVICE_NOT_FOUND; - } - - addr = thunder_pcie_get_cfg_addr(pcie, busnr, devfn, reg); - - switch (len) { - case 1: - *value = readb(addr); - break; - case 2: - *value = readw(addr); - break; - case 4: - *value = readl(addr); - break; - default: - return PCIBIOS_BAD_REGISTER_NUMBER; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int thunder_mmcfg_write_config(struct pci_mmcfg_region *cfg, - unsigned int busnr, unsigned int devfn, int reg, int len, - u32 value) { - struct thunder_pcie *pcie = cfg->data; - void __iomem *addr; - - if (!pcie->valid) { - /* Not support for now */ - pr_err("RC PEM not supported !!!\n"); - return PCIBIOS_DEVICE_NOT_FOUND; - } - - addr = thunder_pcie_get_cfg_addr(pcie, busnr, devfn, reg); - - switch (len) { - case 1: - writeb(value, addr); - break; - case 2: - writew(value, addr); - break; - case 4: - writel(value, addr); - break; - default: - return PCIBIOS_BAD_REGISTER_NUMBER; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int thunder_acpi_mcfg_fixup(struct acpi_pci_root *root, - struct pci_mmcfg_region *cfg) -{ - struct thunder_pcie *pcie; - - pcie = kzalloc(sizeof(*pcie), GFP_KERNEL); - if (!pcie) - return -ENOMEM; - - pcie->dev = &root->device->dev; - - thunder_pcie_config(pcie, cfg->address); - - pcie->cfg_base = cfg->virt; - cfg->data = pcie; - cfg->read = thunder_mmcfg_read_config; - cfg->write = thunder_mmcfg_write_config; - - return 0; -} -DECLARE_ACPI_MCFG_FIXUP("CAVIUM", "THUNDERX", thunder_acpi_mcfg_fixup); -#endif - MODULE_AUTHOR("Sunil Goutham"); MODULE_DESCRIPTION("Cavium Thunder ECAM host controller driver"); MODULE_LICENSE("GPL v2");